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[/] [or1k/] [tags/] [stable_0_2_0/] - Rev 641

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Rev	Log message	Author	Age	Path
641	Modified logging of SPR accesses. Logging only explicit instruction accesses.	ivang	8195d 08h	/or1k/tags/stable_0_2_0/
640	Merge profiler and mprofiler with sim.	ivang	8195d 09h	/or1k/tags/stable_0_2_0/
639	MMU cache inhibit bit test added.	simons	8198d 00h	/or1k/tags/stable_0_2_0/
638	TLBTR CI bit is now working properly.	simons	8198d 00h	/or1k/tags/stable_0_2_0/
637	Updated file names.	lampret	8198d 01h	/or1k/tags/stable_0_2_0/
636	Fixed combinational loops.	lampret	8198d 01h	/or1k/tags/stable_0_2_0/
635	Fixed Makefile bug.	ivang	8198d 03h	/or1k/tags/stable_0_2_0/
634	configure.in : fixed to build start/Makefile start.S : l.jalr r9 -> l.jr r9 Added missing files.	ivang	8199d 04h	/or1k/tags/stable_0_2_0/
633	Bug fix in command line parser.	ivang	8199d 05h	/or1k/tags/stable_0_2_0/
632	profiler and mprofiler merged into sim.	ivang	8200d 00h	/or1k/tags/stable_0_2_0/
631	Real cache access is simulated now.	simons	8200d 23h	/or1k/tags/stable_0_2_0/
630	some bug fixes in store buffer analysis	markom	8201d 08h	/or1k/tags/stable_0_2_0/
629	typo fixed	markom	8201d 12h	/or1k/tags/stable_0_2_0/
627	or32 restored	markom	8201d 12h	/or1k/tags/stable_0_2_0/
626	store buffer added	markom	8201d 12h	/or1k/tags/stable_0_2_0/
625	Bus error bug fixed. Cache routines added.	simons	8202d 04h	/or1k/tags/stable_0_2_0/
624	Added logging of writes/read to/from SPR registers.	ivang	8202d 05h	/or1k/tags/stable_0_2_0/
623	update based on recent changes; arithmetic instructions does not modify carry yet	markom	8202d 07h	/or1k/tags/stable_0_2_0/
622	Cache test works on hardware.	simons	8202d 10h	/or1k/tags/stable_0_2_0/
621	Cache test works on hardware.	simons	8202d 11h	/or1k/tags/stable_0_2_0/

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[/] [or1k/] [tags/] [stable_0_2_0/] - Rev 641

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