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[/] [or1k/] [tags/] [stable_0_2_0/] - Rev 994

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Rev Log message Author Age Path
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 8025d 04h /or1k/tags/stable_0_2_0/
993 Fixed IMMU bug. lampret 8025d 04h /or1k/tags/stable_0_2_0/
992 A bug when cache enabled and bus error comes fixed. simons 8025d 14h /or1k/tags/stable_0_2_0/
991 Different memory controller. simons 8025d 14h /or1k/tags/stable_0_2_0/
990 Test is now complete. simons 8025d 14h /or1k/tags/stable_0_2_0/
989 c++ is making problems so, for now, it is excluded. simons 8026d 22h /or1k/tags/stable_0_2_0/
988 ORP architecture supported. simons 8027d 13h /or1k/tags/stable_0_2_0/
987 ORP architecture supported. simons 8027d 20h /or1k/tags/stable_0_2_0/
986 outputs out of function are not registered anymore markom 8027d 21h /or1k/tags/stable_0_2_0/
985 DTLB translation doesn't work on or1ksim when IC/DC enabled. lampret 8028d 09h /or1k/tags/stable_0_2_0/
984 Disable SB until it is tested lampret 8028d 09h /or1k/tags/stable_0_2_0/
983 First checkin lampret 8028d 11h /or1k/tags/stable_0_2_0/
982 Moved to sim/bin lampret 8028d 11h /or1k/tags/stable_0_2_0/
981 First checkin. lampret 8028d 11h /or1k/tags/stable_0_2_0/
980 Removed sim.tcl that shouldn't be here. lampret 8028d 11h /or1k/tags/stable_0_2_0/
979 Removed old test case binaries. lampret 8028d 11h /or1k/tags/stable_0_2_0/
978 Added variable delay for SRAM. lampret 8028d 11h /or1k/tags/stable_0_2_0/
977 Added store buffer. lampret 8028d 11h /or1k/tags/stable_0_2_0/
976 Added store buffer lampret 8028d 11h /or1k/tags/stable_0_2_0/
975 First checkin lampret 8028d 11h /or1k/tags/stable_0_2_0/

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