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[/] [or1k/] [tags/] [stable_0_2_0/] [or1ksim/] - Rev 642

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Rev Log message Author Age Path
642 Modified logging of SPR accesses. Logging only explicit instruction accesses. ivang 8196d 06h /or1k/tags/stable_0_2_0/or1ksim/
641 Modified logging of SPR accesses. Logging only explicit instruction accesses. ivang 8196d 06h /or1k/tags/stable_0_2_0/or1ksim/
640 Merge profiler and mprofiler with sim. ivang 8196d 07h /or1k/tags/stable_0_2_0/or1ksim/
639 MMU cache inhibit bit test added. simons 8198d 22h /or1k/tags/stable_0_2_0/or1ksim/
638 TLBTR CI bit is now working properly. simons 8198d 22h /or1k/tags/stable_0_2_0/or1ksim/
633 Bug fix in command line parser. ivang 8200d 03h /or1k/tags/stable_0_2_0/or1ksim/
632 profiler and mprofiler merged into sim. ivang 8200d 22h /or1k/tags/stable_0_2_0/or1ksim/
631 Real cache access is simulated now. simons 8201d 21h /or1k/tags/stable_0_2_0/or1ksim/
630 some bug fixes in store buffer analysis markom 8202d 06h /or1k/tags/stable_0_2_0/or1ksim/
629 typo fixed markom 8202d 09h /or1k/tags/stable_0_2_0/or1ksim/
627 or32 restored markom 8202d 10h /or1k/tags/stable_0_2_0/or1ksim/
626 store buffer added markom 8202d 10h /or1k/tags/stable_0_2_0/or1ksim/
624 Added logging of writes/read to/from SPR registers. ivang 8203d 03h /or1k/tags/stable_0_2_0/or1ksim/
623 update based on recent changes; arithmetic instructions does not modify carry yet markom 8203d 05h /or1k/tags/stable_0_2_0/or1ksim/
622 Cache test works on hardware. simons 8203d 08h /or1k/tags/stable_0_2_0/or1ksim/
621 Cache test works on hardware. simons 8203d 09h /or1k/tags/stable_0_2_0/or1ksim/
620 use ARITH_SET_FLAG to turn off set flag by arith. instructions markom 8203d 09h /or1k/tags/stable_0_2_0/or1ksim/
619 all test pass, after newest changes markom 8203d 09h /or1k/tags/stable_0_2_0/or1ksim/
616 flags test added markom 8206d 04h /or1k/tags/stable_0_2_0/or1ksim/
615 cmov and extxx instructions; add, addi, and, andi now set flag markom 8206d 04h /or1k/tags/stable_0_2_0/or1ksim/

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