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[/] [or1k/] [tags/] [stable_0_2_0_rc1/] - Rev 807

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Rev Log message Author Age Path
807 sched files moved to support dir markom 8115d 13h /or1k/tags/stable_0_2_0_rc1/
806 uart now partially uses scheduler markom 8115d 14h /or1k/tags/stable_0_2_0_rc1/
805 kbd, fb, vga devices now uses scheduler markom 8115d 14h /or1k/tags/stable_0_2_0_rc1/
804 memory regions can now overlap with MC -- not according to MC spec markom 8116d 08h /or1k/tags/stable_0_2_0_rc1/
803 Free irq handler fixed. simons 8119d 01h /or1k/tags/stable_0_2_0_rc1/
802 Cache and tick timer tests fixed. simons 8120d 12h /or1k/tags/stable_0_2_0_rc1/
801 l.muli instruction added markom 8122d 08h /or1k/tags/stable_0_2_0_rc1/
800 Bug fixed. simons 8123d 06h /or1k/tags/stable_0_2_0_rc1/
799 Wrapping around 512k boundary to simulate real hw. simons 8126d 23h /or1k/tags/stable_0_2_0_rc1/
798 Hardware scroll added. This possible due to the fact that crt is wrapping around 512k boundary. simons 8126d 23h /or1k/tags/stable_0_2_0_rc1/
797 Changed hardcoded address for fake MC to use a define. lampret 8127d 00h /or1k/tags/stable_0_2_0_rc1/
796 Removed unused ports wb_clki and wb_rst_i lampret 8127d 00h /or1k/tags/stable_0_2_0_rc1/
795 Added a directive to ignore signed division variables that are only used in simulation. lampret 8127d 05h /or1k/tags/stable_0_2_0_rc1/
794 Added again just recently removed full_case directive lampret 8127d 05h /or1k/tags/stable_0_2_0_rc1/
793 Added synthesis off/on for timescale.v included file. lampret 8127d 05h /or1k/tags/stable_0_2_0_rc1/
792 Fixed port names that changed. lampret 8127d 05h /or1k/tags/stable_0_2_0_rc1/
791 Fixed some ports in instnatiations that were removed from the modules lampret 8127d 05h /or1k/tags/stable_0_2_0_rc1/
790 Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives lampret 8127d 05h /or1k/tags/stable_0_2_0_rc1/
789 Added response from memory controller (addr 0x60000000) lampret 8127d 05h /or1k/tags/stable_0_2_0_rc1/
788 Some of the warnings fixed. lampret 8127d 06h /or1k/tags/stable_0_2_0_rc1/

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