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[/] [or1k/] [tags/] [stable_0_2_0_rc1/] - Rev 997

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Rev Log message Author Age Path
997 PRINTF should be used instead of printf; command redirection repaired markom 7977d 16h /or1k/tags/stable_0_2_0_rc1/
996 some minor bugs fixed markom 7978d 15h /or1k/tags/stable_0_2_0_rc1/
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 7978d 23h /or1k/tags/stable_0_2_0_rc1/
993 Fixed IMMU bug. lampret 7978d 23h /or1k/tags/stable_0_2_0_rc1/
992 A bug when cache enabled and bus error comes fixed. simons 7979d 08h /or1k/tags/stable_0_2_0_rc1/
991 Different memory controller. simons 7979d 08h /or1k/tags/stable_0_2_0_rc1/
990 Test is now complete. simons 7979d 08h /or1k/tags/stable_0_2_0_rc1/
989 c++ is making problems so, for now, it is excluded. simons 7980d 16h /or1k/tags/stable_0_2_0_rc1/
988 ORP architecture supported. simons 7981d 07h /or1k/tags/stable_0_2_0_rc1/
987 ORP architecture supported. simons 7981d 15h /or1k/tags/stable_0_2_0_rc1/
986 outputs out of function are not registered anymore markom 7981d 15h /or1k/tags/stable_0_2_0_rc1/
985 DTLB translation doesn't work on or1ksim when IC/DC enabled. lampret 7982d 03h /or1k/tags/stable_0_2_0_rc1/
984 Disable SB until it is tested lampret 7982d 03h /or1k/tags/stable_0_2_0_rc1/
983 First checkin lampret 7982d 05h /or1k/tags/stable_0_2_0_rc1/
982 Moved to sim/bin lampret 7982d 05h /or1k/tags/stable_0_2_0_rc1/
981 First checkin. lampret 7982d 05h /or1k/tags/stable_0_2_0_rc1/
980 Removed sim.tcl that shouldn't be here. lampret 7982d 05h /or1k/tags/stable_0_2_0_rc1/
979 Removed old test case binaries. lampret 7982d 05h /or1k/tags/stable_0_2_0_rc1/
978 Added variable delay for SRAM. lampret 7982d 05h /or1k/tags/stable_0_2_0_rc1/
977 Added store buffer. lampret 7982d 05h /or1k/tags/stable_0_2_0_rc1/

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