OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc1/] [or1ksim/] [testbench/] - Rev 970

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
970 Testbench is now running on ORP architecture platform. simons 7988d 05h /or1k/tags/stable_0_2_0_rc1/or1ksim/testbench/
957 Flash at 0x04000000 RAM at 0x00000000. Only MMU test works. simons 7990d 06h /or1k/tags/stable_0_2_0_rc1/or1ksim/testbench/
956 Changed to work with or32-uclinux tool chain. Everything works except keyboard test. simons 7990d 11h /or1k/tags/stable_0_2_0_rc1/or1ksim/testbench/
915 cuc main verilog file generation markom 8004d 12h /or1k/tags/stable_0_2_0_rc1/or1ksim/testbench/
909 Bug fix. lampret 8006d 05h /or1k/tags/stable_0_2_0_rc1/or1ksim/testbench/
889 Modified Ethernet model. ivang 8022d 08h /or1k/tags/stable_0_2_0_rc1/or1ksim/testbench/
840 Added execution of pre and post simulation shell scripts.
Script should be named <testname>.pre.sh for pre-execution script
and <testname>.post.sh for post-execution script.
ivang 8099d 14h /or1k/tags/stable_0_2_0_rc1/or1ksim/testbench/
838 Bug fix. ivang 8100d 07h /or1k/tags/stable_0_2_0_rc1/or1ksim/testbench/
837 Configuration for ethernet testcase. ivang 8100d 10h /or1k/tags/stable_0_2_0_rc1/or1ksim/testbench/
836 Fixed bug in file interface. Modified testcase to suid modifications. ivang 8100d 10h /or1k/tags/stable_0_2_0_rc1/or1ksim/testbench/
826 or32-uclinux target added markom 8107d 16h /or1k/tags/stable_0_2_0_rc1/or1ksim/testbench/
802 Cache and tick timer tests fixed. simons 8120d 17h /or1k/tags/stable_0_2_0_rc1/or1ksim/testbench/
733 Fixed configuration. ivang 8148d 11h /or1k/tags/stable_0_2_0_rc1/or1ksim/testbench/
730 tick section is now obsolete; update your .cfg files! markom 8149d 16h /or1k/tags/stable_0_2_0_rc1/or1ksim/testbench/
715 dhrystones strcmp repaired markom 8151d 18h /or1k/tags/stable_0_2_0_rc1/or1ksim/testbench/
705 Updated changed registers. ivang 8157d 13h /or1k/tags/stable_0_2_0_rc1/or1ksim/testbench/
702 Initial coding of ethernet simulator model finished. ivang 8157d 18h /or1k/tags/stable_0_2_0_rc1/or1ksim/testbench/
699 Simprintf bug fixed again. simons 8162d 06h /or1k/tags/stable_0_2_0_rc1/or1ksim/testbench/
698 Simprintf bug fixed again. simons 8162d 06h /or1k/tags/stable_0_2_0_rc1/or1ksim/testbench/
697 Simprintf bug fixed again. simons 8162d 06h /or1k/tags/stable_0_2_0_rc1/or1ksim/testbench/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.