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[/] [or1k/] [tags/] [stable_0_2_0_rc2/] - Rev 1022

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Rev Log message Author Age Path
1022 As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy. lampret 7984d 03h /or1k/tags/stable_0_2_0_rc2/
1021 *** empty log message *** rherveille 7988d 06h /or1k/tags/stable_0_2_0_rc2/
1020 Fixed several bugs
Working version, tested on Bender hardware		 rherveille 7988d 06h /or1k/tags/stable_0_2_0_rc2/
1019 fixed some bugs detected by Bender hardware rherveille 7988d 06h /or1k/tags/stable_0_2_0_rc2/
1018 TX_BD_NUM register now contains a real number of transmit BDs (before this was n*2) simons 7988d 12h /or1k/tags/stable_0_2_0_rc2/
1017 TX_BD_NUM register now contains a real number of transmit BDs (before this was n*2) simons 7988d 13h /or1k/tags/stable_0_2_0_rc2/
1016 64 bytes is the smallest packet size. simons 7989d 05h /or1k/tags/stable_0_2_0_rc2/
1015 Host type was not recognized. simons 7989d 15h /or1k/tags/stable_0_2_0_rc2/
1014 added _JBLEN definition for or1k ivang 7990d 04h /or1k/tags/stable_0_2_0_rc2/
1013 ORP architecture supported. simons 7990d 07h /or1k/tags/stable_0_2_0_rc2/
1011 Removed some commented RTL. Fixed SR/ESR flag bug. lampret 7991d 00h /or1k/tags/stable_0_2_0_rc2/
1010 Import ivang 7995d 03h /or1k/tags/stable_0_2_0_rc2/
1009 Import ivang 7995d 03h /or1k/tags/stable_0_2_0_rc2/
1008 Import ivang 7995d 04h /or1k/tags/stable_0_2_0_rc2/
1007 Import ivang 7995d 04h /or1k/tags/stable_0_2_0_rc2/
1006 Import ivang 7995d 04h /or1k/tags/stable_0_2_0_rc2/
1005 Import ivang 7995d 04h /or1k/tags/stable_0_2_0_rc2/
1004 Now every ramdisk image should have init program. simons 7995d 12h /or1k/tags/stable_0_2_0_rc2/
1003 cuc temporary files are deleted upon exiting markom 7995d 12h /or1k/tags/stable_0_2_0_rc2/
1002 Now every ramdisk image should have init program. simons 7995d 13h /or1k/tags/stable_0_2_0_rc2/

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