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[/] [or1k/] [tags/] [stable_0_2_0_rc2/] - Rev 411

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Rev Log message Author Age Path
411 acv uart testsuite now works (without modem test) markom 8281d 10h /or1k/tags/stable_0_2_0_rc2/
410 MMU test added. simons 8282d 04h /or1k/tags/stable_0_2_0_rc2/
409 some minor changes to or1ksim; Testbench except.s modified. Interrupt test almost finished for uart ACV. markom 8282d 10h /or1k/tags/stable_0_2_0_rc2/
408 Fixed errant rx_bd_num erez 8283d 06h /or1k/tags/stable_0_2_0_rc2/
406 Renamed ethernet's RX_BD_ADR to RX_BD_NUM erez 8283d 09h /or1k/tags/stable_0_2_0_rc2/
405 Stepping trough l.jal and l.jalr fixed. simons 8284d 10h /or1k/tags/stable_0_2_0_rc2/
404 is_delayed() is used outside this file. simons 8284d 10h /or1k/tags/stable_0_2_0_rc2/
403 Prompt changed because ddd requires (gdb). simons 8284d 10h /or1k/tags/stable_0_2_0_rc2/
402 Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32 lampret 8284d 15h /or1k/tags/stable_0_2_0_rc2/
401 *** empty log message *** simons 8288d 01h /or1k/tags/stable_0_2_0_rc2/
400 force_dslot_fetch does not work - allways zero. simons 8288d 01h /or1k/tags/stable_0_2_0_rc2/
399 Trap insn couses break after exits ex_insn. simons 8288d 01h /or1k/tags/stable_0_2_0_rc2/
398 added register field defines ivang 8290d 06h /or1k/tags/stable_0_2_0_rc2/
397 removed or16 architecture markom 8290d 08h /or1k/tags/stable_0_2_0_rc2/
396 added missing file markom 8290d 10h /or1k/tags/stable_0_2_0_rc2/
395 removed obsolete dependency and history from cpu section markom 8290d 12h /or1k/tags/stable_0_2_0_rc2/
394 dependency joined with dependstats; history moved to sim section markom 8290d 13h /or1k/tags/stable_0_2_0_rc2/
393 messages: exception on many places changed to abort markom 8290d 13h /or1k/tags/stable_0_2_0_rc2/
391 Fixed except_stop width and fixed EX PC for 1400444f no-ops. lampret 8290d 21h /or1k/tags/stable_0_2_0_rc2/
390 Changed instantiation name of VS RAMs. lampret 8290d 23h /or1k/tags/stable_0_2_0_rc2/

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