OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc2/] [or1ksim/] - Rev 12

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
12 Added information to the section about how to configure and compile
the package.
jrydberg 8950d 05h /or1k/tags/stable_0_2_0_rc2/or1ksim/
11 Rebuild from configure.in. jrydberg 8950d 05h /or1k/tags/stable_0_2_0_rc2/or1ksim/
10 Support for both architectures. Specify architecture with the
--target option.
jrydberg 8950d 05h /or1k/tags/stable_0_2_0_rc2/or1ksim/
9 Added support for OpenRISC 100 and DLX. jrydberg 8950d 05h /or1k/tags/stable_0_2_0_rc2/or1ksim/
8 Initial revision. jrydberg 8950d 05h /or1k/tags/stable_0_2_0_rc2/or1ksim/
7 Major update of the enviorment. Now uses autoconf and automake. The
simulator uses readline aswell to get input from the user. A number of
new files added, some modified. The libc directory is now called support.
jrydberg 8950d 05h /or1k/tags/stable_0_2_0_rc2/or1ksim/
6 Just a regular update with exception of cache simulation. MMU simulation still under development. lampret 8950d 23h /or1k/tags/stable_0_2_0_rc2/or1ksim/
5 Data and instruction cache simulation added. lampret 8950d 23h /or1k/tags/stable_0_2_0_rc2/or1ksim/
4 no message lampret 9001d 03h /or1k/tags/stable_0_2_0_rc2/or1ksim/
3 This commit was generated by cvs2svn to compensate for changes in r2, which
included commits to RCS files with non-trunk default branches.
cvs 9076d 16h /or1k/tags/stable_0_2_0_rc2/or1ksim/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.