URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc2/] [or1ksim/] [cpu/] [common/] - Rev 28

Rev	Log message	Author	Age	Path
28	Adding COFF loader.	lampret	8814d 21h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/common/
26	Clean up.	lampret	8830d 18h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/common/
25	Bug fix in handling labels when loading code into simulator memory.	lampret	8830d 18h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/common/
24	Static branch prediction added.	lampret	8830d 18h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/common/
22	More modifications related to or16.	lampret	8833d 00h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/common/
18	or16 added, or1k renamed to or32.	lampret	8833d 14h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/common/
13	Rebuild of the generated files.	jrydberg	8894d 06h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/common/
7	Major update of the enviorment. Now uses autoconf and automake. The simulator uses readline aswell to get input from the user. A number of new files added, some modified. The libc directory is now called support.	jrydberg	8894d 06h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/common/
6	Just a regular update with exception of cache simulation. MMU simulation still under development.	lampret	8895d 00h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/common/
3	This commit was generated by cvs2svn to compensate for changes in r2, which included commits to RCS files with non-trunk default branches.	cvs	9020d 18h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/common/