OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc2/] [or1ksim/] [cpu/] [or1k/] - Rev 1471

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
1471 Rewrite the interactive mode handling to also work in the recompiler nogj 7064d 00h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1452 Implement a dynamic recompiler to speed up the execution nogj 7064d 00h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1446 Cosmetic fixes nogj 7064d 00h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1444 Move the definitions needed for the simple execution model out of or32.h and into simpl32_defs.h nogj 7064d 00h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1442 Replace some problematic calles to mfspr/mtspr with direct access to the spr nogj 7064d 00h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1432 Collect most of the cpu state variables in a structure (cpu_state) nogj 7064d 01h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1404 Move the function of ic_clock() to mtspr() and remove it nogj 7064d 01h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1402 Do what dc_clock() did in mtspr() and remove it nogj 7064d 01h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1386 Rework exception handling nogj 7070d 04h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1382 Nir Mor:
Implemented DCCFGR, ICCFGR, DMMUCFGR and IMMUCFGR spr registers.		 nogj 7079d 04h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1376 aclocal && autoconf && automake phoenix 7098d 05h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1354 typing fixes phoenix 7113d 02h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7113d 23h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1344 * Avoid doing a store in *every* instruction executed by storeing the instruction function unit in or32_opcodes nogj 7127d 03h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1342 * Fix generate.c to produce a execgen.c with less warnings.
* Fix the --enable-simple configure option.		 nogj 7127d 03h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1341 Mark wich operand is the destination operand in the architechture definition nogj 7127d 03h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1338 l.ff1 instruction added andreje 7143d 01h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1319 cpu/sim memory accesses separation, tick, exception, nr. of operands, cycles count,... corrections. phoenix 7230d 18h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1316 added a warning phoenix 7248d 15h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
1314 in some cases (cbasic test from orp for example) this caused problems, disable for now phoenix 7248d 16h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.