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[/] [or1k/] [tags/] [stable_0_2_0_rc2/] [or1ksim/] [cpu/] [or1k/] - Rev 615

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Rev Log message Author Age Path
615 cmov and extxx instructions; add, addi, and, andi now set flag markom 8219d 19h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
600 No more low/high priority interrupts (PICPR removed). Added tick timer exception. simons 8225d 11h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
599 No more low/high priority interrupts (PICPR removed). Added tick timer exception. simons 8225d 11h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
572 Some new bugs fixed. simons 8230d 13h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
561 Tick timer is not connected to PIC. simons 8231d 17h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
556 support for SPR_SR_EP added; cpu.sr added to config markom 8235d 02h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
535 stats is updated; statical single stats removed; t command output cleaned, added time output; cycles is moved to instructions; cycles now count time markom 8237d 19h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
518 some more performance optimizations markom 8240d 19h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
517 some performance optimizations markom 8240d 20h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
515 uart test updated; simprintf updated markom 8241d 00h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
511 new reporting system markom 8241d 19h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
510 new reporting system markom 8241d 19h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
500 Added .cvsignore files for annoying generated files erez 8243d 00h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
479 connection with gdb repaired; temp_except_delay removed; lot of except and debug code cleaned; sys 203 causes stall under gdb; non-sim memory area log bug fixed markom 8256d 20h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
464 Some small bugs fixed. simons 8257d 12h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
458 Align, bus error and range exception fixed. simons 8258d 12h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
450 Exceptions are allways enabled. simons 8262d 00h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
447 ITLBMR register bit fields set in order. simons 8263d 02h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
446 ITLBMR register bit fields set in order. simons 8263d 02h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/
437 When lsu instruction produce exception registers are preserved. simons 8263d 20h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/

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