OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc2/] [or1ksim/] [cpu/] [or32/] - Rev 1482

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
1482 Fix instruction counter nogj 7037d 05h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or32/
1481 Remove the useless cross reference stuff: it was a bad idea to begin with nogj 7037d 05h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or32/
1475 l.rfe does not have a delay slot. Don't mark it as such. nogj 7037d 05h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or32/
1474 * Building op.S and op.o depend on op_t_reg_mov_op.h
* Clean generated files produced by the recompiler		 nogj 7037d 05h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or32/
1471 Rewrite the interactive mode handling to also work in the recompiler nogj 7064d 08h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or32/
1452 Implement a dynamic recompiler to speed up the execution nogj 7064d 08h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or32/
1446 Cosmetic fixes nogj 7064d 09h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or32/
1444 Move the definitions needed for the simple execution model out of or32.h and into simpl32_defs.h nogj 7064d 09h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or32/
1442 Replace some problematic calles to mfspr/mtspr with direct access to the spr nogj 7064d 09h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or32/
1440 Reclasify l.trap and l.sys to be an exception instruction nogj 7064d 09h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or32/
1438 NOP_REPORT should report numbers in hex not decimal nogj 7064d 09h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or32/
1432 Collect most of the cpu state variables in a structure (cpu_state) nogj 7064d 09h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or32/
1430 Log SPR_SR in the execution log nogj 7064d 09h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or32/
1428 Remove useless indirection: check_depend()->depend_operands() nogj 7064d 09h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or32/
1386 Rework exception handling nogj 7070d 12h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or32/
1384 Fix the parameters to the l.ff1/l.maci instructions nogj 7079d 12h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or32/
1376 aclocal && autoconf && automake phoenix 7098d 13h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or32/
1375 Remove FAST_SIM, it nolonger provides a speed up nogj 7105d 04h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or32/
1352 Optimise execution history tracking nogj 7114d 07h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or32/
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7114d 07h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or32/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.