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[/] [or1k/] [tags/] [stable_0_2_0_rc3/] - Rev 1624

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Rev Log message Author Age Path
1624 First Import of uClinux for RC20x board jcastillo 6836d 12h /or1k/tags/stable_0_2_0_rc3/
1623 First Import of uClinux for RC20x board jcastillo 6836d 12h /or1k/tags/stable_0_2_0_rc3/
1622 First Import of uClinux for RC20x board jcastillo 6836d 12h /or1k/tags/stable_0_2_0_rc3/
1621 First Impot jcastillo 6836d 13h /or1k/tags/stable_0_2_0_rc3/
1620 Added SMC91C111 LAN Chip Interruption to work with uClinux jcastillo 6841d 09h /or1k/tags/stable_0_2_0_rc3/
1619 Fixed types in function declaration jcastillo 6841d 14h /or1k/tags/stable_0_2_0_rc3/
1618 Import of or32 sepcific part of binutils port updated by Balint and Nog phoenix 6841d 21h /or1k/tags/stable_0_2_0_rc3/
1617 *** empty log message *** phoenix 6841d 21h /or1k/tags/stable_0_2_0_rc3/
1616 Import of or32 sepcific part of binutils port updated by Balint and Nog phoenix 6841d 21h /or1k/tags/stable_0_2_0_rc3/
1615 *** empty log message *** phoenix 6841d 21h /or1k/tags/stable_0_2_0_rc3/
1614 CI should not be set in dMMU translation tables or one gets different behaviour with dMMU on or off in case data cache is enabled. care should be taken for addresses higher than 0x7fff_ffff where the situation is just reversed. (since or1200 does not cache upper half of address space if there is no dMMU) phoenix 6851d 22h /or1k/tags/stable_0_2_0_rc3/
1613 change default phoenix 6857d 07h /or1k/tags/stable_0_2_0_rc3/
1612 major optimizations for or32 target phoenix 6857d 08h /or1k/tags/stable_0_2_0_rc3/
1610 Update ChangeLog nogj 6860d 09h /or1k/tags/stable_0_2_0_rc3/
1609 0.2.0-rc2 release nogj 6860d 09h /or1k/tags/stable_0_2_0_rc3/
1608 Avoid scheduleing too many jobs, potentially underflowing the scheduler stack nogj 6861d 03h /or1k/tags/stable_0_2_0_rc3/
1607 Don't drop cycles from the scheduler nogj 6861d 03h /or1k/tags/stable_0_2_0_rc3/
1606 fix uninitialized reads phoenix 6861d 08h /or1k/tags/stable_0_2_0_rc3/
1605 Execute l.ff1 instruction nogj 6868d 04h /or1k/tags/stable_0_2_0_rc3/
1604 Fix dumphex/dumpverilog to not do unaligned memory access nogj 6868d 04h /or1k/tags/stable_0_2_0_rc3/

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