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[/] [or1k/] [tags/] [stable_0_2_0_rc3/] - Rev 400

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Rev Log message Author Age Path
400 force_dslot_fetch does not work - allways zero. simons 8260d 23h /or1k/tags/stable_0_2_0_rc3/
399 Trap insn couses break after exits ex_insn. simons 8260d 23h /or1k/tags/stable_0_2_0_rc3/
398 added register field defines ivang 8263d 04h /or1k/tags/stable_0_2_0_rc3/
397 removed or16 architecture markom 8263d 05h /or1k/tags/stable_0_2_0_rc3/
396 added missing file markom 8263d 07h /or1k/tags/stable_0_2_0_rc3/
395 removed obsolete dependency and history from cpu section markom 8263d 09h /or1k/tags/stable_0_2_0_rc3/
394 dependency joined with dependstats; history moved to sim section markom 8263d 11h /or1k/tags/stable_0_2_0_rc3/
393 messages: exception on many places changed to abort markom 8263d 11h /or1k/tags/stable_0_2_0_rc3/
391 Fixed except_stop width and fixed EX PC for 1400444f no-ops. lampret 8263d 19h /or1k/tags/stable_0_2_0_rc3/
390 Changed instantiation name of VS RAMs. lampret 8263d 20h /or1k/tags/stable_0_2_0_rc3/
389 Changed default delay for load and store in superscalar cpu. lampret 8263d 21h /or1k/tags/stable_0_2_0_rc3/
388 Added comments for cpu section. lampret 8263d 21h /or1k/tags/stable_0_2_0_rc3/
387 Now FPGA and ASIC target are separate. lampret 8263d 22h /or1k/tags/stable_0_2_0_rc3/
386 Fixed VS RAM instantiation - again. lampret 8263d 22h /or1k/tags/stable_0_2_0_rc3/
385 check testbench now modified to work with new report output markom 8264d 04h /or1k/tags/stable_0_2_0_rc3/
384 modified simmem.cfg structure! ADD > BEFORE EACH LINE! markom 8264d 05h /or1k/tags/stable_0_2_0_rc3/
383 modified simmem.cfg structure! ADD markom 8264d 05h /or1k/tags/stable_0_2_0_rc3/
382 bitmask function bug fixed markom 8264d 07h /or1k/tags/stable_0_2_0_rc3/
381 number display is more strict with 0x prefix with hex numbers markom 8264d 07h /or1k/tags/stable_0_2_0_rc3/
380 all tests pass check markom 8264d 08h /or1k/tags/stable_0_2_0_rc3/

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