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[/] [or1k/] [tags/] [stable_0_2_0_rc3/] - Rev 632

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Rev Log message Author Age Path
632 profiler and mprofiler merged into sim. ivang 8186d 09h /or1k/tags/stable_0_2_0_rc3/
631 Real cache access is simulated now. simons 8187d 08h /or1k/tags/stable_0_2_0_rc3/
630 some bug fixes in store buffer analysis markom 8187d 17h /or1k/tags/stable_0_2_0_rc3/
629 typo fixed markom 8187d 21h /or1k/tags/stable_0_2_0_rc3/
627 or32 restored markom 8187d 21h /or1k/tags/stable_0_2_0_rc3/
626 store buffer added markom 8187d 21h /or1k/tags/stable_0_2_0_rc3/
625 Bus error bug fixed. Cache routines added. simons 8188d 14h /or1k/tags/stable_0_2_0_rc3/
624 Added logging of writes/read to/from SPR registers. ivang 8188d 14h /or1k/tags/stable_0_2_0_rc3/
623 update based on recent changes; arithmetic instructions does not modify carry yet markom 8188d 16h /or1k/tags/stable_0_2_0_rc3/
622 Cache test works on hardware. simons 8188d 19h /or1k/tags/stable_0_2_0_rc3/
621 Cache test works on hardware. simons 8188d 20h /or1k/tags/stable_0_2_0_rc3/
620 use ARITH_SET_FLAG to turn off set flag by arith. instructions markom 8188d 20h /or1k/tags/stable_0_2_0_rc3/
619 all test pass, after newest changes markom 8188d 20h /or1k/tags/stable_0_2_0_rc3/
618 Fixed display of new 'void' nop insns. lampret 8189d 05h /or1k/tags/stable_0_2_0_rc3/
617 Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. lampret 8189d 05h /or1k/tags/stable_0_2_0_rc3/
616 flags test added markom 8191d 15h /or1k/tags/stable_0_2_0_rc3/
615 cmov and extxx instructions; add, addi, and, andi now set flag markom 8191d 15h /or1k/tags/stable_0_2_0_rc3/
614 Changed to support new debug if. simons 8191d 22h /or1k/tags/stable_0_2_0_rc3/
613 init: trap exception occurs always; initialization of sr not needed anymore markom 8192d 20h /or1k/tags/stable_0_2_0_rc3/
612 Tick timer period extended to meet real timing. simons 8192d 21h /or1k/tags/stable_0_2_0_rc3/

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