OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc3/] [or1ksim/] [bpb/] - Rev 970

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
970 Testbench is now running on ORP architecture platform. simons 8063d 12h /or1k/tags/stable_0_2_0_rc3/or1ksim/bpb/
876 Beta release of ATA simulation rherveille 8107d 11h /or1k/tags/stable_0_2_0_rc3/or1ksim/bpb/
541 lot of new parameters concerning memory delays added; bpb parameter moved from cpu to new bpb section; UPDATE YOUR .CFG FILES! markom 8282d 21h /or1k/tags/stable_0_2_0_rc3/or1ksim/bpb/
517 some performance optimizations markom 8286d 20h /or1k/tags/stable_0_2_0_rc3/or1ksim/bpb/
500 Added .cvsignore files for annoying generated files erez 8289d 00h /or1k/tags/stable_0_2_0_rc3/or1ksim/bpb/
306 corrected lots of bugs markom 8344d 00h /or1k/tags/stable_0_2_0_rc3/or1ksim/bpb/
264 updated cpu config section; added sim config section markom 8349d 20h /or1k/tags/stable_0_2_0_rc3/or1ksim/bpb/
221 major changes to testbench; debug unit is moved to /debug; memory organization can be customized; UART from simons; overall cleanup markom 8358d 23h /or1k/tags/stable_0_2_0_rc3/or1ksim/bpb/
102 Major update to include PM, PIC, Cache Mngmnt and non-interactive mode. lampret 8518d 05h /or1k/tags/stable_0_2_0_rc3/or1ksim/bpb/
54 Regular maintenance. lampret 8788d 02h /or1k/tags/stable_0_2_0_rc3/or1ksim/bpb/
28 Adding COFF loader. lampret 8879d 09h /or1k/tags/stable_0_2_0_rc3/or1ksim/bpb/
26 Clean up. lampret 8895d 06h /or1k/tags/stable_0_2_0_rc3/or1ksim/bpb/
18 or16 added, or1k renamed to or32. lampret 8898d 02h /or1k/tags/stable_0_2_0_rc3/or1ksim/bpb/
13 Rebuild of the generated files. jrydberg 8958d 18h /or1k/tags/stable_0_2_0_rc3/or1ksim/bpb/
7 Major update of the enviorment. Now uses autoconf and automake. The
simulator uses readline aswell to get input from the user. A number of
new files added, some modified. The libc directory is now called support.		 jrydberg 8958d 18h /or1k/tags/stable_0_2_0_rc3/or1ksim/bpb/
6 Just a regular update with exception of cache simulation. MMU simulation still under development. lampret 8959d 12h /or1k/tags/stable_0_2_0_rc3/or1ksim/bpb/
3 This commit was generated by cvs2svn to compensate for changes in r2, which
included commits to RCS files with non-trunk default branches.		 cvs 9085d 06h /or1k/tags/stable_0_2_0_rc3/or1ksim/bpb/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.