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[/] [or1k/] [tags/] [stable_0_2_0_rc3/] [or1ksim/] [cpu/] [or32/] - Rev 129

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Rev Log message Author Age Path
129 Added code to inject insn from Debug Unit DIR chris 8429d 06h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu/or32/
123 Bugs fixed:
- l.rfe temporarly disables exceptions
- l.sys does PC -= 4
- breakpoints now supported at peripheria locations
- uart0.rt/.tx nonexistent file segment fault

Other modifications:
- replaced string names to instruction indexes
- execute.c executes specified (in ISA table) function
- modified ISA table - flag needed for gdb
- added or32.c, which supports or32.h
- added new instructions l.mac, l.msb, l.maci, l.macrc
and their executing functions (opcodes to be revisited)
- added header acconfig.h
- modified configuration files		 markom 8435d 04h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu/or32/
102 Major update to include PM, PIC, Cache Mngmnt and non-interactive mode. lampret 8460d 13h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu/or32/
98 Return value register is now r9. lampret 8475d 13h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu/or32/
83 Updates. lampret 8507d 04h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu/or32/
77 Regular update. lampret 8660d 10h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu/or32/
68 Added hook for l.sys 204. Changed SPR of flag (no more CCR) lampret 8679d 10h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu/or32/
54 Regular maintenance. lampret 8730d 10h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu/or32/
20 or1k renamed to or32. lampret 8840d 09h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu/or32/
13 Rebuild of the generated files. jrydberg 8901d 02h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu/or32/
7 Major update of the enviorment. Now uses autoconf and automake. The
simulator uses readline aswell to get input from the user. A number of
new files added, some modified. The libc directory is now called support.		 jrydberg 8901d 02h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu/or32/
6 Just a regular update with exception of cache simulation. MMU simulation still under development. lampret 8901d 20h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu/or32/
3 This commit was generated by cvs2svn to compensate for changes in r2, which
included commits to RCS files with non-trunk default branches.		 cvs 9027d 14h /or1k/tags/stable_0_2_0_rc3/or1ksim/cpu/or32/

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