OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [tn_m001/] [or1ksim/] - Rev 25

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
25 Bug fix in handling labels when loading code into simulator memory. lampret 8828d 01h /or1k/tags/tn_m001/or1ksim/
24 Static branch prediction added. lampret 8828d 01h /or1k/tags/tn_m001/or1ksim/
23 Common OR1K backend for OR32 and OR16. lampret 8828d 01h /or1k/tags/tn_m001/or1ksim/
22 More modifications related to or16. lampret 8830d 07h /or1k/tags/tn_m001/or1ksim/
21 More modifications related to or16. cmchen 8830d 07h /or1k/tags/tn_m001/or1ksim/
20 or1k renamed to or32. lampret 8830d 20h /or1k/tags/tn_m001/or1ksim/
19 Added or16, or1k renamed to or32. lampret 8830d 21h /or1k/tags/tn_m001/or1ksim/
18 or16 added, or1k renamed to or32. lampret 8830d 21h /or1k/tags/tn_m001/or1ksim/
17 Re-generated. jrydberg 8853d 17h /or1k/tags/tn_m001/or1ksim/
16 Add support for systems without readline. To use GNU readline library,
use the `--enable-readline' option to the configure script.		 jrydberg 8853d 17h /or1k/tags/tn_m001/or1ksim/
15 Initial revision. jrydberg 8890d 08h /or1k/tags/tn_m001/or1ksim/
13 Rebuild of the generated files. jrydberg 8891d 13h /or1k/tags/tn_m001/or1ksim/
12 Added information to the section about how to configure and compile
the package.		 jrydberg 8891d 13h /or1k/tags/tn_m001/or1ksim/
11 Rebuild from configure.in. jrydberg 8891d 13h /or1k/tags/tn_m001/or1ksim/
10 Support for both architectures. Specify architecture with the
--target option.		 jrydberg 8891d 13h /or1k/tags/tn_m001/or1ksim/
9 Added support for OpenRISC 100 and DLX. jrydberg 8891d 13h /or1k/tags/tn_m001/or1ksim/
8 Initial revision. jrydberg 8891d 13h /or1k/tags/tn_m001/or1ksim/
7 Major update of the enviorment. Now uses autoconf and automake. The
simulator uses readline aswell to get input from the user. A number of
new files added, some modified. The libc directory is now called support.		 jrydberg 8891d 13h /or1k/tags/tn_m001/or1ksim/
6 Just a regular update with exception of cache simulation. MMU simulation still under development. lampret 8892d 07h /or1k/tags/tn_m001/or1ksim/
5 Data and instruction cache simulation added. lampret 8892d 07h /or1k/tags/tn_m001/or1ksim/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.