OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [tn_m001/] [or1ksim/] - Rev 68

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
68 Added hook for l.sys 204. Changed SPR of flag (no more CCR) lampret 8669d 11h /or1k/tags/tn_m001/or1ksim/
67 Added simulator "application load". lampret 8669d 11h /or1k/tags/tn_m001/or1ksim/
66 Added another set of eval_ functions that should be used directly by simulator.
evalsim_ and setsim_ don't go through MMU transaltion mechanism.		 lampret 8669d 11h /or1k/tags/tn_m001/or1ksim/
65 Added DMMU stats. lampret 8669d 11h /or1k/tags/tn_m001/or1ksim/
64 SPR bit definition moved to spr_defs.h. lampret 8669d 11h /or1k/tags/tn_m001/or1ksim/
63 Fixed a bug in getsprbits/setsprbits functions (now mask can have arbitry
alignment of bits).		 lampret 8669d 11h /or1k/tags/tn_m001/or1ksim/
62 OR1K DMMU model. lampret 8669d 11h /or1k/tags/tn_m001/or1ksim/
60 Memory model changed. lampret 8704d 14h /or1k/tags/tn_m001/or1ksim/
55 Added 'dv' command for dumping memory as verilog model. lampret 8720d 11h /or1k/tags/tn_m001/or1ksim/
54 Regular maintenance. lampret 8720d 11h /or1k/tags/tn_m001/or1ksim/
52 Comment character changed. lampret 8781d 07h /or1k/tags/tn_m001/or1ksim/
51 Exception detection changed a bit. lampret 8781d 07h /or1k/tags/tn_m001/or1ksim/
50 Added CURINSN macro. lampret 8781d 07h /or1k/tags/tn_m001/or1ksim/
49 Changed simulation mode to non-virtual (real). lampret 8781d 07h /or1k/tags/tn_m001/or1ksim/
48 Added CCR. lampret 8781d 07h /or1k/tags/tn_m001/or1ksim/
47 Added interrupt recognition and better memory dump. lampret 8781d 07h /or1k/tags/tn_m001/or1ksim/
46 Added srand(). lampret 8781d 07h /or1k/tags/tn_m001/or1ksim/
45 Added NONE. lampret 8781d 07h /or1k/tags/tn_m001/or1ksim/
44 %s bug fixed. lampret 8786d 12h /or1k/tags/tn_m001/or1ksim/
43 SUPV bit from SR is now saved into EPCR bit 0. lampret 8791d 16h /or1k/tags/tn_m001/or1ksim/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.