OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] - Rev 1194

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
1194 correct all the syntax errors dries 7738d 02h /or1k/trunk/
1193 disabled SRAM_GENERIC and added comment +
corrected 'wb_err' into 'wb_err_o'
dries 7738d 03h /or1k/trunk/
1192 disabled 'bench_defines.v' during synthesis +
added define to specify usage of flash instruction address
dries 7738d 04h /or1k/trunk/
1191 disabled 'bench_defines.v' during synthesis +
added define to specify usage of flash instruction address
dries 7738d 04h /or1k/trunk/
1188 Added support for rams with byte write access. simons 7754d 03h /or1k/trunk/
1186 Added support for rams with byte write access. simons 7755d 02h /or1k/trunk/
1184 Scan signals mess fixed. simons 7761d 19h /or1k/trunk/
1183 OpenRISC port of gdb-5.3 straightforwardly derived from gdb-5.0 sfurman 7766d 10h /or1k/trunk/
1181 Initial import of unmodified gdb-5.3 source on vendor branch sfurman 7766d 13h /or1k/trunk/
1179 BIST interface added for Artisan memory instances. simons 7769d 22h /or1k/trunk/
1178 avoid another immu exception that should not happen phoenix 7799d 10h /or1k/trunk/
1177 more informative output phoenix 7800d 16h /or1k/trunk/
1176 Added comments. damonb 7801d 07h /or1k/trunk/
1174 fix for immu exceptions that never should have happened phoenix 7802d 11h /or1k/trunk/
1170 Added support for l.addc instruction. csanchez 7810d 15h /or1k/trunk/
1169 Added support for l.addc instruction. csanchez 7810d 16h /or1k/trunk/
1168 Added explicit alignment expressions. csanchez 7816d 02h /or1k/trunk/
1167 Corrected offset of TSS field within task_struct. csanchez 7816d 02h /or1k/trunk/
1166 Fixed problem with relocations of non-allocated sections. csanchez 7816d 02h /or1k/trunk/
1165 timeout bug fixed; contribution by Carlos markom 7832d 20h /or1k/trunk/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.