URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] - Rev 203

Rev	Log message	Author	Age	Path
203	Updated from xess branch.	lampret	8320d 03h	/or1k/trunk/
202	changed configure.in and acconfig.h to check for long long reran autoheader & autoconf	erez	8325d 10h	/or1k/trunk/
201	readfunc() and writefunc() now use unsigned long values instead of unsigned char.	erez	8325d 10h	/or1k/trunk/
200	Initial import	simons	8328d 17h	/or1k/trunk/
199	Initial import	simons	8328d 19h	/or1k/trunk/
198	Moved from testbench.old	simons	8331d 06h	/or1k/trunk/
197	This is not used any more.	simons	8331d 06h	/or1k/trunk/
196	Configuration SPRs added.	simons	8331d 06h	/or1k/trunk/
195	New test added.	simons	8331d 06h	/or1k/trunk/
194	Fixed a bug for little endian architectures. Could cause a hang of gdb under some circumstances.	chris	8331d 14h	/or1k/trunk/
193	Declared RISCOP.RESET to be volatile so that -O2 optimization would not optimize away the correct behavior by trying to be too clever.	chris	8331d 14h	/or1k/trunk/
192	Removed GlobalMode reference causing problems for --disable-debugmod option.	chris	8331d 23h	/or1k/trunk/
191	Added UART jitter var to sim config	chris	8332d 20h	/or1k/trunk/
190	Added jitter initialization	chris	8332d 20h	/or1k/trunk/
189	fixed mode handling for tick facility	chris	8332d 20h	/or1k/trunk/
188	fixed PIC interrupt controller	chris	8332d 20h	/or1k/trunk/
187	minor change to clear pending exception	chris	8332d 20h	/or1k/trunk/
186	major change to UART structure	chris	8332d 20h	/or1k/trunk/
185	major change to UART code	chris	8332d 20h	/or1k/trunk/
184	modified decode for trace debugging	chris	8332d 20h	/or1k/trunk/