OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] - Rev 361

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
361 set config command added; config struct has been divided into two structs - config and runtime; -f option allows multiple config scripts markom 8267d 20h /or1k/trunk/
360 Added OR1200_REGISTERED_INPUTS. lampret 8268d 07h /or1k/trunk/
359 Added optional sampling of inputs. lampret 8268d 07h /or1k/trunk/
358 Fixed virtual silicon single-port rams instantiation. lampret 8268d 07h /or1k/trunk/
357 Fixed dbg_is_o assignment width. lampret 8268d 07h /or1k/trunk/
356 Break point bug fixed simons 8268d 10h /or1k/trunk/
355 uart VAPI model improved; changes to MC and eth. markom 8268d 17h /or1k/trunk/
354 Fixed width of du_except. lampret 8269d 03h /or1k/trunk/
353 Cashes disabled. simons 8269d 14h /or1k/trunk/
352 OR1200_REGISTERED_OUTPUTS can now be enabled. lampret 8270d 17h /or1k/trunk/
351 Fixed some l.trap typos. lampret 8270d 18h /or1k/trunk/
350 For GDB changed single stepping and disabled trap exception. lampret 8270d 20h /or1k/trunk/
349 Some bugs regarding cache simulation fixed. simons 8272d 08h /or1k/trunk/
348 Added instructions on how to build configure. ivang 8273d 16h /or1k/trunk/
347 Added CRC32 calculation to Ethernet erez 8274d 13h /or1k/trunk/
346 Improved Ethernet simulation erez 8274d 15h /or1k/trunk/
345 Added check for net/ethernet.h (needed by ethernet simulator) erez 8274d 15h /or1k/trunk/
344 added acv test for uart; sim debug now has verbose levels; lot of bugs fixed in uart model markom 8274d 17h /or1k/trunk/
343 Small touches to test programs erez 8274d 19h /or1k/trunk/
342 added exception vectors to support and modified section names markom 8275d 16h /or1k/trunk/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.