OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] - Rev 403

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
403 Prompt changed because ddd requires (gdb). simons 8235d 21h /or1k/trunk/
402 Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32 lampret 8236d 02h /or1k/trunk/
401 *** empty log message *** simons 8239d 12h /or1k/trunk/
400 force_dslot_fetch does not work - allways zero. simons 8239d 12h /or1k/trunk/
399 Trap insn couses break after exits ex_insn. simons 8239d 12h /or1k/trunk/
398 added register field defines ivang 8241d 17h /or1k/trunk/
397 removed or16 architecture markom 8241d 18h /or1k/trunk/
396 added missing file markom 8241d 20h /or1k/trunk/
395 removed obsolete dependency and history from cpu section markom 8241d 22h /or1k/trunk/
394 dependency joined with dependstats; history moved to sim section markom 8242d 00h /or1k/trunk/
393 messages: exception on many places changed to abort markom 8242d 00h /or1k/trunk/
391 Fixed except_stop width and fixed EX PC for 1400444f no-ops. lampret 8242d 07h /or1k/trunk/
390 Changed instantiation name of VS RAMs. lampret 8242d 09h /or1k/trunk/
389 Changed default delay for load and store in superscalar cpu. lampret 8242d 09h /or1k/trunk/
388 Added comments for cpu section. lampret 8242d 09h /or1k/trunk/
387 Now FPGA and ASIC target are separate. lampret 8242d 11h /or1k/trunk/
386 Fixed VS RAM instantiation - again. lampret 8242d 11h /or1k/trunk/
385 check testbench now modified to work with new report output markom 8242d 17h /or1k/trunk/
384 modified simmem.cfg structure! ADD > BEFORE EACH LINE! markom 8242d 18h /or1k/trunk/
383 modified simmem.cfg structure! ADD markom 8242d 18h /or1k/trunk/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.