URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] - Rev 994

Rev	Log message	Author	Age	Path
994	Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.	lampret	7988d 04h	/or1k/trunk/
993	Fixed IMMU bug.	lampret	7988d 04h	/or1k/trunk/
992	A bug when cache enabled and bus error comes fixed.	simons	7988d 13h	/or1k/trunk/
991	Different memory controller.	simons	7988d 13h	/or1k/trunk/
990	Test is now complete.	simons	7988d 13h	/or1k/trunk/
989	c++ is making problems so, for now, it is excluded.	simons	7989d 21h	/or1k/trunk/
988	ORP architecture supported.	simons	7990d 12h	/or1k/trunk/
987	ORP architecture supported.	simons	7990d 20h	/or1k/trunk/
986	outputs out of function are not registered anymore	markom	7990d 20h	/or1k/trunk/
985	DTLB translation doesn't work on or1ksim when IC/DC enabled.	lampret	7991d 08h	/or1k/trunk/
984	Disable SB until it is tested	lampret	7991d 08h	/or1k/trunk/
983	First checkin	lampret	7991d 10h	/or1k/trunk/
982	Moved to sim/bin	lampret	7991d 10h	/or1k/trunk/
981	First checkin.	lampret	7991d 10h	/or1k/trunk/
980	Removed sim.tcl that shouldn't be here.	lampret	7991d 10h	/or1k/trunk/
979	Removed old test case binaries.	lampret	7991d 10h	/or1k/trunk/
978	Added variable delay for SRAM.	lampret	7991d 10h	/or1k/trunk/
977	Added store buffer.	lampret	7991d 10h	/or1k/trunk/
976	Added store buffer	lampret	7991d 10h	/or1k/trunk/
975	First checkin	lampret	7991d 10h	/or1k/trunk/