URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] - Rev 998

Rev	Log message	Author	Age	Path
998	added missing fout initialization	markom	7986d 19h	/or1k/trunk/
997	PRINTF should be used instead of printf; command redirection repaired	markom	7986d 20h	/or1k/trunk/
996	some minor bugs fixed	markom	7987d 19h	/or1k/trunk/
994	Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.	lampret	7988d 02h	/or1k/trunk/
993	Fixed IMMU bug.	lampret	7988d 03h	/or1k/trunk/
992	A bug when cache enabled and bus error comes fixed.	simons	7988d 12h	/or1k/trunk/
991	Different memory controller.	simons	7988d 12h	/or1k/trunk/
990	Test is now complete.	simons	7988d 12h	/or1k/trunk/
989	c++ is making problems so, for now, it is excluded.	simons	7989d 20h	/or1k/trunk/
988	ORP architecture supported.	simons	7990d 11h	/or1k/trunk/
987	ORP architecture supported.	simons	7990d 19h	/or1k/trunk/
986	outputs out of function are not registered anymore	markom	7990d 19h	/or1k/trunk/
985	DTLB translation doesn't work on or1ksim when IC/DC enabled.	lampret	7991d 07h	/or1k/trunk/
984	Disable SB until it is tested	lampret	7991d 07h	/or1k/trunk/
983	First checkin	lampret	7991d 09h	/or1k/trunk/
982	Moved to sim/bin	lampret	7991d 09h	/or1k/trunk/
981	First checkin.	lampret	7991d 09h	/or1k/trunk/
980	Removed sim.tcl that shouldn't be here.	lampret	7991d 09h	/or1k/trunk/
979	Removed old test case binaries.	lampret	7991d 09h	/or1k/trunk/
978	Added variable delay for SRAM.	lampret	7991d 09h	/or1k/trunk/