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[/] [or1k/] [trunk/] [gen_or1k_isa/] - Rev 1672

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Rev	Log message	Author	Age	Path
1672	Store instructions don't modify any register. Don't mark them as such in the arch. definitions	nogj	6794d 05h	/or1k/trunk/gen_or1k_isa/
1656	Pass the instruction operands as part of the op_queue structure.	nogj	6794d 06h	/or1k/trunk/gen_or1k_isa/
1605	Execute l.ff1 instruction	nogj	6856d 07h	/or1k/trunk/gen_or1k_isa/
1601	fixed description of l.sfXXXi	lampret	6858d 10h	/or1k/trunk/gen_or1k_isa/
1597	Fix parsing the destination register	nogj	6868d 09h	/or1k/trunk/gen_or1k_isa/
1591	Added l.fl1, fixed desc of l.ff1	lampret	6871d 06h	/or1k/trunk/gen_or1k_isa/
1590	Added l.fl1	lampret	6871d 06h	/or1k/trunk/gen_or1k_isa/
1557	Fix most warnings issued by gcc4	nogj	6930d 16h	/or1k/trunk/gen_or1k_isa/
1554	fixed l.maci encoding	phoenix	6948d 03h	/or1k/trunk/gen_or1k_isa/
1475	l.rfe does not have a delay slot. Don't mark it as such.	nogj	7061d 06h	/or1k/trunk/gen_or1k_isa/
1452	Implement a dynamic recompiler to speed up the execution	nogj	7088d 09h	/or1k/trunk/gen_or1k_isa/
1440	Reclasify l.trap and l.sys to be an exception instruction	nogj	7088d 09h	/or1k/trunk/gen_or1k_isa/
1385	Fix description of the l.mac/l.msb/l.maci instructions	nogj	7103d 13h	/or1k/trunk/gen_or1k_isa/
1384	Fix the parameters to the l.ff1/l.maci instructions	nogj	7103d 13h	/or1k/trunk/gen_or1k_isa/
1350	Mark a simulated cpu address as such, by introducing the new oraddr_t type	nogj	7138d 07h	/or1k/trunk/gen_or1k_isa/
1346	Remove the global op structure	nogj	7151d 11h	/or1k/trunk/gen_or1k_isa/
1342	* Fix generate.c to produce a execgen.c with less warnings. * Fix the --enable-simple configure option.	nogj	7151d 11h	/or1k/trunk/gen_or1k_isa/
1341	Mark wich operand is the destination operand in the architechture definition	nogj	7151d 12h	/or1k/trunk/gen_or1k_isa/
1338	l.ff1 instruction added	andreje	7167d 09h	/or1k/trunk/gen_or1k_isa/
1309	removed includes	phoenix	7340d 05h	/or1k/trunk/gen_or1k_isa/

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[/] [or1k/] [trunk/] [gen_or1k_isa/] - Rev 1672

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