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[/] [or1k/] [trunk/] [or1200/] [rtl/] [verilog/] - Rev 1022

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Rev Log message Author Age Path
1022 As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy. lampret 8009d 00h /or1k/trunk/or1200/rtl/verilog/
1011 Removed some commented RTL. Fixed SR/ESR flag bug. lampret 8015d 20h /or1k/trunk/or1200/rtl/verilog/
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 8021d 20h /or1k/trunk/or1200/rtl/verilog/
993 Fixed IMMU bug. lampret 8021d 20h /or1k/trunk/or1200/rtl/verilog/
984 Disable SB until it is tested lampret 8025d 00h /or1k/trunk/or1200/rtl/verilog/
977 Added store buffer. lampret 8025d 02h /or1k/trunk/or1200/rtl/verilog/
962 Fixed Xilinx trace buffer address. REported by Taylor Su. lampret 8028d 16h /or1k/trunk/or1200/rtl/verilog/
958 Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run. lampret 8029d 16h /or1k/trunk/or1200/rtl/verilog/
944 Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section. lampret 8031d 16h /or1k/trunk/or1200/rtl/verilog/
943 Added optional retry counter for wb_rty_i. Added graceful termination for aborted transfers. lampret 8031d 16h /or1k/trunk/or1200/rtl/verilog/
942 Delayed external access at page crossing. lampret 8031d 16h /or1k/trunk/or1200/rtl/verilog/
916 MAC now follows software convention (signed multiply instead of unsigned). lampret 8043d 20h /or1k/trunk/or1200/rtl/verilog/
895 Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. lampret 8060d 00h /or1k/trunk/or1200/rtl/verilog/
871 Generic flip-flop based memory macro for register file. lampret 8096d 06h /or1k/trunk/or1200/rtl/verilog/
870 Added defines for enabling generic FF based memory macro for register file. lampret 8096d 06h /or1k/trunk/or1200/rtl/verilog/
869 Added generic flip-flop based memory macro instantiation. lampret 8096d 06h /or1k/trunk/or1200/rtl/verilog/
795 Added a directive to ignore signed division variables that are only used in simulation. lampret 8167d 05h /or1k/trunk/or1200/rtl/verilog/
794 Added again just recently removed full_case directive lampret 8167d 05h /or1k/trunk/or1200/rtl/verilog/
791 Fixed some ports in instnatiations that were removed from the modules lampret 8167d 06h /or1k/trunk/or1200/rtl/verilog/
790 Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives lampret 8167d 06h /or1k/trunk/or1200/rtl/verilog/

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