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[/] [or1k/] [trunk/] [or1ksim/] [cpu/] [dlx/] - Rev 879

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Rev Log message Author Age Path
879 Initial version of OpenRISC Custom Unit Compiler added markom 8031d 04h /or1k/trunk/or1ksim/cpu/dlx/
538 memory width increased to 32bit; new memory test mem_test added - simple big endian test markom 8208d 11h /or1k/trunk/or1ksim/cpu/dlx/
500 Added .cvsignore files for annoying generated files erez 8214d 10h /or1k/trunk/or1ksim/cpu/dlx/
393 messages: exception on many places changed to abort markom 8249d 14h /or1k/trunk/or1ksim/cpu/dlx/
247 Major update of the enviorment. Now uses autoconf and automake. The
simulator uses readline aswell to get input from the user. A number of
new files added, some modified. The libc directory is now called support.		 jrydberg 8279d 16h /or1k/trunk/or1ksim/cpu/dlx/
245 Initial revision cvs 8279d 16h /or1k/trunk/or1ksim/cpu/dlx/
221 major changes to testbench; debug unit is moved to /debug; memory organization can be customized; UART from simons; overall cleanup markom 8284d 10h /or1k/trunk/or1ksim/cpu/dlx/
123 Bugs fixed:
- l.rfe temporarly disables exceptions
- l.sys does PC -= 4
- breakpoints now supported at peripheria locations
- uart0.rt/.tx nonexistent file segment fault

Other modifications:
- replaced string names to instruction indexes
- execute.c executes specified (in ISA table) function
- modified ISA table - flag needed for gdb
- added or32.c, which supports or32.h
- added new instructions l.mac, l.msb, l.maci, l.macrc
and their executing functions (opcodes to be revisited)
- added header acconfig.h
- modified configuration files		 markom 8418d 07h /or1k/trunk/or1ksim/cpu/dlx/
77 Regular update. lampret 8643d 13h /or1k/trunk/or1ksim/cpu/dlx/
30 Updated SPRs, exceptions. Added 16450 device. lampret 8789d 22h /or1k/trunk/or1ksim/cpu/dlx/
26 Clean up. lampret 8820d 17h /or1k/trunk/or1ksim/cpu/dlx/
18 or16 added, or1k renamed to or32. lampret 8823d 12h /or1k/trunk/or1ksim/cpu/dlx/
8 Initial revision. jrydberg 8884d 05h /or1k/trunk/or1ksim/cpu/dlx/
6 Just a regular update with exception of cache simulation. MMU simulation still under development. lampret 8884d 23h /or1k/trunk/or1ksim/cpu/dlx/
3 This commit was generated by cvs2svn to compensate for changes in r2, which
included commits to RCS files with non-trunk default branches.		 cvs 9010d 16h /or1k/trunk/or1ksim/cpu/dlx/

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