URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [orp/] - Rev 1096

Rev	Log message	Author	Age	Path
1096	An example of SW and RTL regression log because many people asked for.	lampret	7914d 10h	/or1k/trunk/orp/
1094	sys/time.h might not be available for or1k target	lampret	7915d 07h	/or1k/trunk/orp/
1093	New UART rx/tx fiel settings (due to or1ksim upgrade)	lampret	7915d 07h	/or1k/trunk/orp/
1092	Changed from or32-rtems toolchain to or32-uclinux.	lampret	7915d 08h	/or1k/trunk/orp/
1091	Added mmu test.	lampret	7915d 08h	/or1k/trunk/orp/
1090	Removed ic_invalidate	lampret	7915d 08h	/or1k/trunk/orp/
1089	Added dhrystone 2.1 benchmark	lampret	7915d 08h	/or1k/trunk/orp/
1088	Changed from or32-rtems toolchain to or32-uclinux.	lampret	7915d 08h	/or1k/trunk/orp/
1087	Changed or32-rtems to or32-uclinux.	lampret	7915d 08h	/or1k/trunk/orp/
1057	Different memory controller.	simons	7985d 13h	/or1k/trunk/orp/
1052	Delayed wb_err_o. Disabled wb_ack_o when wb_err_o is asserted.	lampret	7986d 07h	/or1k/trunk/orp/
991	Different memory controller.	simons	8011d 16h	/or1k/trunk/orp/
990	Test is now complete.	simons	8011d 17h	/or1k/trunk/orp/
985	DTLB translation doesn't work on or1ksim when IC/DC enabled.	lampret	8014d 11h	/or1k/trunk/orp/
983	First checkin	lampret	8014d 14h	/or1k/trunk/orp/
982	Moved to sim/bin	lampret	8014d 14h	/or1k/trunk/orp/
981	First checkin.	lampret	8014d 14h	/or1k/trunk/orp/
980	Removed sim.tcl that shouldn't be here.	lampret	8014d 14h	/or1k/trunk/orp/
979	Removed old test case binaries.	lampret	8014d 14h	/or1k/trunk/orp/
978	Added variable delay for SRAM.	lampret	8014d 14h	/or1k/trunk/orp/