URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [orp/] [orp_soc/] - Rev 1096

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
1096	An example of SW and RTL regression log because many people asked for.	lampret	7892d 05h	/or1k/trunk/orp/orp_soc/
1094	sys/time.h might not be available for or1k target	lampret	7893d 03h	/or1k/trunk/orp/orp_soc/
1093	New UART rx/tx fiel settings (due to or1ksim upgrade)	lampret	7893d 03h	/or1k/trunk/orp/orp_soc/
1092	Changed from or32-rtems toolchain to or32-uclinux.	lampret	7893d 03h	/or1k/trunk/orp/orp_soc/
1091	Added mmu test.	lampret	7893d 03h	/or1k/trunk/orp/orp_soc/
1090	Removed ic_invalidate	lampret	7893d 03h	/or1k/trunk/orp/orp_soc/
1089	Added dhrystone 2.1 benchmark	lampret	7893d 03h	/or1k/trunk/orp/orp_soc/
1088	Changed from or32-rtems toolchain to or32-uclinux.	lampret	7893d 03h	/or1k/trunk/orp/orp_soc/
1087	Changed or32-rtems to or32-uclinux.	lampret	7893d 03h	/or1k/trunk/orp/orp_soc/
1057	Different memory controller.	simons	7963d 08h	/or1k/trunk/orp/orp_soc/
1052	Delayed wb_err_o. Disabled wb_ack_o when wb_err_o is asserted.	lampret	7964d 02h	/or1k/trunk/orp/orp_soc/
991	Different memory controller.	simons	7989d 12h	/or1k/trunk/orp/orp_soc/
990	Test is now complete.	simons	7989d 12h	/or1k/trunk/orp/orp_soc/
985	DTLB translation doesn't work on or1ksim when IC/DC enabled.	lampret	7992d 07h	/or1k/trunk/orp/orp_soc/
983	First checkin	lampret	7992d 09h	/or1k/trunk/orp/orp_soc/
982	Moved to sim/bin	lampret	7992d 09h	/or1k/trunk/orp/orp_soc/
981	First checkin.	lampret	7992d 09h	/or1k/trunk/orp/orp_soc/
980	Removed sim.tcl that shouldn't be here.	lampret	7992d 09h	/or1k/trunk/orp/orp_soc/
979	Removed old test case binaries.	lampret	7992d 09h	/or1k/trunk/orp/orp_soc/
978	Added variable delay for SRAM.	lampret	7992d 09h	/or1k/trunk/orp/orp_soc/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories or1k

[/] [or1k/] [trunk/] [orp/] [orp_soc/] - Rev 1096

Filtering Options