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[/] [or1k/] [trunk/] [orp/] [orp_soc/] - Rev 1192

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Rev Log message Author Age Path
1192 disabled 'bench_defines.v' during synthesis +
added define to specify usage of flash instruction address		 dries 7695d 21h /or1k/trunk/orp/orp_soc/
1191 disabled 'bench_defines.v' during synthesis +
added define to specify usage of flash instruction address		 dries 7695d 21h /or1k/trunk/orp/orp_soc/
1176 Added comments. damonb 7759d 01h /or1k/trunk/orp/orp_soc/
1158 Added simple uart test case. lampret 7838d 06h /or1k/trunk/orp/orp_soc/
1157 Added syscall test case. lampret 7838d 06h /or1k/trunk/orp/orp_soc/
1156 Tick timer test case added. lampret 7839d 02h /or1k/trunk/orp/orp_soc/
1141 WB = 1/2 RISC clock test code enabled. lampret 7853d 07h /or1k/trunk/orp/orp_soc/
1138 Added some information how to run simulations. lampret 7854d 03h /or1k/trunk/orp/orp_soc/
1137 Added RFRAM generic and Altera lpm library. lampret 7854d 03h /or1k/trunk/orp/orp_soc/
1136 Add altera lpm library. lampret 7854d 03h /or1k/trunk/orp/orp_soc/
1135 Added get_gpr support for OR1200_RFRAM_GENERIC lampret 7854d 03h /or1k/trunk/orp/orp_soc/
1134 Changed location of debug test code to 0. lampret 7854d 03h /or1k/trunk/orp/orp_soc/
1133 Adding OR1200_CLMODE_1TO2 test code. lampret 7854d 03h /or1k/trunk/orp/orp_soc/
1125 This test case passes. lampret 7875d 09h /or1k/trunk/orp/orp_soc/
1105 Added WB b3 signals lampret 7973d 19h /or1k/trunk/orp/orp_soc/
1096 An example of SW and RTL regression log because many people asked for. lampret 7985d 05h /or1k/trunk/orp/orp_soc/
1094 sys/time.h might not be available for or1k target lampret 7986d 02h /or1k/trunk/orp/orp_soc/
1093 New UART rx/tx fiel settings (due to or1ksim upgrade) lampret 7986d 02h /or1k/trunk/orp/orp_soc/
1092 Changed from or32-rtems toolchain to or32-uclinux. lampret 7986d 03h /or1k/trunk/orp/orp_soc/
1091 Added mmu test. lampret 7986d 03h /or1k/trunk/orp/orp_soc/

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