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[/] [or1k/] [trunk/] [orp/] [orp_soc/] [sim/] - Rev 1780

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Rev	Log message	Author	Age	Path
1765		root	5573d 21h	/or1k/trunk/orp/orp_soc/sim/
1271	Merged branch_qmem into main tree.	lampret	7374d 10h	/or1k/trunk/orp/orp_soc/sim/
1158	Added simple uart test case.	lampret	7722d 21h	/or1k/trunk/orp/orp_soc/sim/
1157	Added syscall test case.	lampret	7722d 21h	/or1k/trunk/orp/orp_soc/sim/
1156	Tick timer test case added.	lampret	7723d 17h	/or1k/trunk/orp/orp_soc/sim/
1137	Added RFRAM generic and Altera lpm library.	lampret	7738d 18h	/or1k/trunk/orp/orp_soc/sim/
1105	Added WB b3 signals	lampret	7858d 10h	/or1k/trunk/orp/orp_soc/sim/
1096	An example of SW and RTL regression log because many people asked for.	lampret	7869d 20h	/or1k/trunk/orp/orp_soc/sim/
1087	Changed or32-rtems to or32-uclinux.	lampret	7870d 18h	/or1k/trunk/orp/orp_soc/sim/
983	First checkin	lampret	7969d 23h	/or1k/trunk/orp/orp_soc/sim/
982	Moved to sim/bin	lampret	7969d 23h	/or1k/trunk/orp/orp_soc/sim/
981	First checkin.	lampret	7969d 23h	/or1k/trunk/orp/orp_soc/sim/
980	Removed sim.tcl that shouldn't be here.	lampret	7969d 23h	/or1k/trunk/orp/orp_soc/sim/
979	Removed old test case binaries.	lampret	7969d 23h	/or1k/trunk/orp/orp_soc/sim/
976	Added store buffer	lampret	7970d 00h	/or1k/trunk/orp/orp_soc/sim/
975	First checkin	lampret	7970d 00h	/or1k/trunk/orp/orp_soc/sim/
961	uart16550 RTL files renamed/added/removed.	lampret	7973d 14h	/or1k/trunk/orp/orp_soc/sim/
952	Added or1200_monitor top.	lampret	7976d 14h	/or1k/trunk/orp/orp_soc/sim/
951	Updated file names	lampret	7976d 14h	/or1k/trunk/orp/orp_soc/sim/
950	Removed nop.log. Added general.log and lookup.log. In the middle of moving test cases.	lampret	7976d 14h	/or1k/trunk/orp/orp_soc/sim/

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[/] [or1k/] [trunk/] [orp/] [orp_soc/] [sim/] - Rev 1780

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