OpenCores
URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

Subversion Repositories or1k_old

[/] [or1k_old/] [tags/] [rel_15/] - Rev 1782

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
1782 root 5452d 01h /or1k_old/tags/rel_15/
1765 root 5562d 17h /or1k_old/tags/rel_15/
1201 This commit was manufactured by cvs2svn to create tag 'rel_15'. 7534d 08h /or1k_old/tags/rel_15/
1200 mbist signals updated according to newest convention markom 7534d 08h /or1k_old/tags/rel_15/
1199 Daniel Wiklund: Removed multiple entries of debug/Makefile in configure danwi 7538d 08h /or1k_old/tags/rel_15/
1198 make it compile on RH 8,9 phoenix 7563d 23h /or1k_old/tags/rel_15/
1197 disabled ram-init of ps2 (old) +
changed MAC type into DOS type, so that Xilinx ISE can work with it		 dries 7569d 04h /or1k_old/tags/rel_15/
1196 removed second debug/Makefile (credits: Daniel Wiklund - danwi@isy.liu.se) dries 7569d 05h /or1k_old/tags/rel_15/
1195 made the project file a little bit more universal dries 7569d 06h /or1k_old/tags/rel_15/
1194 correct all the syntax errors dries 7569d 06h /or1k_old/tags/rel_15/
1193 disabled SRAM_GENERIC and added comment +
corrected 'wb_err' into 'wb_err_o'		 dries 7569d 07h /or1k_old/tags/rel_15/
1192 disabled 'bench_defines.v' during synthesis +
added define to specify usage of flash instruction address		 dries 7569d 08h /or1k_old/tags/rel_15/
1191 disabled 'bench_defines.v' during synthesis +
added define to specify usage of flash instruction address		 dries 7569d 08h /or1k_old/tags/rel_15/
1188 Added support for rams with byte write access. simons 7585d 07h /or1k_old/tags/rel_15/
1186 Added support for rams with byte write access. simons 7586d 06h /or1k_old/tags/rel_15/
1184 Scan signals mess fixed. simons 7592d 23h /or1k_old/tags/rel_15/
1183 OpenRISC port of gdb-5.3 straightforwardly derived from gdb-5.0 sfurman 7597d 14h /or1k_old/tags/rel_15/
1181 Initial import of unmodified gdb-5.3 source on vendor branch sfurman 7597d 17h /or1k_old/tags/rel_15/
1179 BIST interface added for Artisan memory instances. simons 7601d 02h /or1k_old/tags/rel_15/
1178 avoid another immu exception that should not happen phoenix 7630d 14h /or1k_old/tags/rel_15/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.