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[/] [or1k_old/] [trunk/] [or1200/] [rtl/] - Rev 1782

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Rev Log message Author Age Path
1782 root 5460d 10h /or1k_old/trunk/or1200/rtl/
1765 root 5571d 02h /or1k_old/trunk/or1200/rtl/
1736 See OR1200_MAC_SHIFTBY in or1200_defines.v for explanation of the change. Since now no more 28 bits shift for l.macrc insns however for backward compatbility it is possible to set arbitry number of shifts. lampret 6637d 23h /or1k_old/trunk/or1200/rtl/
1583 First Import jcastillo 6809d 13h /or1k_old/trunk/or1200/rtl/
1582 Added support for RAMB16 Xilinx4/Spartan3 primitives jcastillo 6809d 13h /or1k_old/trunk/or1200/rtl/
1339 revert to the old l.sfxxi behavior phoenix 7088d 14h /or1k_old/trunk/or1200/rtl/
1337 du_hwbkpt disabled when debug unit not implemented andreje 7094d 15h /or1k_old/trunk/or1200/rtl/
1336 sign/zero extension for l.sfxxi instructions corrected andreje 7094d 15h /or1k_old/trunk/or1200/rtl/
1335 flag for l.cmov instruction added andreje 7094d 15h /or1k_old/trunk/or1200/rtl/
1334 l.ff1 and l.cmov instructions added andreje 7094d 16h /or1k_old/trunk/or1200/rtl/
1293 Non-functional changes. Coding style fixes. lampret 7307d 07h /or1k_old/trunk/or1200/rtl/
1292 GPR0 hardwired to zero. lampret 7307d 07h /or1k_old/trunk/or1200/rtl/
1291 Changed behavior of the simulation generic models lampret 7307d 07h /or1k_old/trunk/or1200/rtl/
1288 By default l.cust5 insns are disabled lampret 7337d 05h /or1k_old/trunk/or1200/rtl/
1284 Added some l.cust5 custom instructions as example lampret 7337d 05h /or1k_old/trunk/or1200/rtl/
1273 Add support for 512B instruction cache. simont 7368d 14h /or1k_old/trunk/or1200/rtl/
1268 Merged branch_qmem into main tree. lampret 7371d 16h /or1k_old/trunk/or1200/rtl/
1267 Merged branch_qmem into main tree. lampret 7371d 16h /or1k_old/trunk/or1200/rtl/
1228 Exception prefix configuration changed to match branch_qmem configuration. simons 7452d 16h /or1k_old/trunk/or1200/rtl/
1211 New wb_biu for iwb interface. lampret 7494d 01h /or1k_old/trunk/or1200/rtl/

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