URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

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[/] [or1k_old/] [trunk/] [orp/] - Rev 1158

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Rev	Log message	Author	Age	Path
1158	Added simple uart test case.	lampret	7746d 12h	/or1k_old/trunk/orp/
1157	Added syscall test case.	lampret	7746d 12h	/or1k_old/trunk/orp/
1156	Tick timer test case added.	lampret	7747d 09h	/or1k_old/trunk/orp/
1141	WB = 1/2 RISC clock test code enabled.	lampret	7761d 14h	/or1k_old/trunk/orp/
1138	Added some information how to run simulations.	lampret	7762d 09h	/or1k_old/trunk/orp/
1137	Added RFRAM generic and Altera lpm library.	lampret	7762d 09h	/or1k_old/trunk/orp/
1136	Add altera lpm library.	lampret	7762d 09h	/or1k_old/trunk/orp/
1135	Added get_gpr support for OR1200_RFRAM_GENERIC	lampret	7762d 09h	/or1k_old/trunk/orp/
1134	Changed location of debug test code to 0.	lampret	7762d 09h	/or1k_old/trunk/orp/
1133	Adding OR1200_CLMODE_1TO2 test code.	lampret	7762d 09h	/or1k_old/trunk/orp/
1125	This test case passes.	lampret	7783d 15h	/or1k_old/trunk/orp/
1105	Added WB b3 signals	lampret	7882d 02h	/or1k_old/trunk/orp/
1096	An example of SW and RTL regression log because many people asked for.	lampret	7893d 11h	/or1k_old/trunk/orp/
1094	sys/time.h might not be available for or1k target	lampret	7894d 09h	/or1k_old/trunk/orp/
1093	New UART rx/tx fiel settings (due to or1ksim upgrade)	lampret	7894d 09h	/or1k_old/trunk/orp/
1092	Changed from or32-rtems toolchain to or32-uclinux.	lampret	7894d 09h	/or1k_old/trunk/orp/
1091	Added mmu test.	lampret	7894d 09h	/or1k_old/trunk/orp/
1090	Removed ic_invalidate	lampret	7894d 09h	/or1k_old/trunk/orp/
1089	Added dhrystone 2.1 benchmark	lampret	7894d 09h	/or1k_old/trunk/orp/
1088	Changed from or32-rtems toolchain to or32-uclinux.	lampret	7894d 09h	/or1k_old/trunk/orp/

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Subversion Repositories or1k_old

[/] [or1k_old/] [trunk/] [orp/] - Rev 1158

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