URL https://opencores.org/ocsvn/pairing/pairing/trunk

Subversion Repositories pairing

[/] [pairing/] - Rev 24

Rev	Log message	Author	Age	Path
24	LGPL claim in each source hdl file	homer.xing	4495d 07h	/pairing/
23	LGPL license text	homer.xing	4495d 07h	/pairing/
22	Change TAB to space	homer.xing	4495d 09h	/pairing/
21	Add detailed input data capture condition in the document	homer.xing	4495d 09h	/pairing/
20	Add a module and a testbench for Xilinx ISE post-route simulation	homer.xing	4496d 11h	/pairing/
19	Update synthesis result	homer.xing	4497d 05h	/pairing/
18	add synthesis result	homer.xing	4497d 05h	/pairing/
17	use logic for $f3m_mux6$	homer.xing	4497d 06h	/pairing/
16	Add synthesis configuration files	homer.xing	4497d 09h	/pairing/
15	add document. ha ha ha	homer.xing	4497d 11h	/pairing/
14	Move constraint file	homer.xing	4497d 11h	/pairing/
13	Add document and synthesis directories	homer.xing	4497d 11h	/pairing/
12	Simplify the interface of the core.	homer.xing	4497d 12h	/pairing/
11	Cheers! as fast as a rocket	homer.xing	4498d 08h	/pairing/
10	Ho ho, better circuit	homer.xing	4499d 02h	/pairing/
9	Add constrains file for ISE	homer.xing	4500d 05h	/pairing/
8	Finished Tate Pairing. Ha ha ha	homer.xing	4500d 06h	/pairing/
7	Finish inversion @ f33m	homer.xing	4508d 11h	/pairing/
6	add testbench for $f33m$.	homer.xing	4509d 11h	/pairing/
5	rename director : verilog/ -> rtl/	homer.xing	4509d 11h	/pairing/