URL https://opencores.org/ocsvn/pairing/pairing/trunk

Subversion Repositories pairing

[/] [pairing/] [trunk/] - Rev 27

Rev	Log message	Author	Age	Path
27	definition for undefined wire	homer.xing	4646d 12h	/pairing/trunk/
26	Detailed description for the ModelSim macro file and the main test bench file	homer.xing	4652d 08h	/pairing/trunk/
25	simulation scripts and readme-file explaining how to start the simulation	homer.xing	4652d 08h	/pairing/trunk/
24	LGPL claim in each source hdl file	homer.xing	4660d 08h	/pairing/trunk/
23	LGPL license text	homer.xing	4660d 08h	/pairing/trunk/
22	Change TAB to space	homer.xing	4660d 10h	/pairing/trunk/
21	Add detailed input data capture condition in the document	homer.xing	4660d 10h	/pairing/trunk/
20	Add a module and a testbench for Xilinx ISE post-route simulation	homer.xing	4661d 12h	/pairing/trunk/
19	Update synthesis result	homer.xing	4662d 06h	/pairing/trunk/
18	add synthesis result	homer.xing	4662d 06h	/pairing/trunk/
17	use logic for $f3m_mux6$	homer.xing	4662d 07h	/pairing/trunk/
16	Add synthesis configuration files	homer.xing	4662d 11h	/pairing/trunk/
15	add document. ha ha ha	homer.xing	4662d 12h	/pairing/trunk/
14	Move constraint file	homer.xing	4662d 12h	/pairing/trunk/
13	Add document and synthesis directories	homer.xing	4662d 12h	/pairing/trunk/
12	Simplify the interface of the core.	homer.xing	4662d 13h	/pairing/trunk/
11	Cheers! as fast as a rocket	homer.xing	4663d 09h	/pairing/trunk/
10	Ho ho, better circuit	homer.xing	4664d 03h	/pairing/trunk/
9	Add constrains file for ISE	homer.xing	4665d 06h	/pairing/trunk/
8	Finished Tate Pairing. Ha ha ha	homer.xing	4665d 07h	/pairing/trunk/