OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [asyst_2/] - Rev 115

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
115 Added signals for WB Master B3. tadejm 7624d 02h /pci/tags/asyst_2/
113 ifdefs moved to thier own lines, this confuses some of the tools. simons 7631d 05h /pci/tags/asyst_2/
111 synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. simons 7631d 10h /pci/tags/asyst_2/
110 Module that converts slave WISHBONE B3 accesses to
WISHBONE B2 accesses with CAB.		 mihad 7633d 09h /pci/tags/asyst_2/
109 There was missing path to hdl.var file. tadejm 7637d 07h /pci/tags/asyst_2/
108 Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. tadejm 7637d 07h /pci/tags/asyst_2/
107 Added status when checking disconnect with or without data. Before it was only retry, now there is stop and retry. tadejm 7637d 07h /pci/tags/asyst_2/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7642d 05h /pci/tags/asyst_2/
105 Wrong pci_bridge32.v file included in the project! mihad 7647d 12h /pci/tags/asyst_2/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7647d 15h /pci/tags/asyst_2/
103 Added test application and modified files to support it. mihad 7694d 12h /pci/tags/asyst_2/
102 Cleanup! mihad 7694d 12h /pci/tags/asyst_2/
101 Added simulation files. mihad 7694d 12h /pci/tags/asyst_2/
100 Cleanup! mihad 7694d 12h /pci/tags/asyst_2/
99 Cleanup! mihad 7694d 13h /pci/tags/asyst_2/
98 Cleanup. mihad 7694d 13h /pci/tags/asyst_2/
97 Doing a little bit of cleanup. mihad 7694d 13h /pci/tags/asyst_2/
96 Update! mihad 7694d 13h /pci/tags/asyst_2/
95 Removed this file, because it was too large - long download time. mihad 7694d 13h /pci/tags/asyst_2/
94 Changed one critical PCI bus signal logic. mihad 7694d 13h /pci/tags/asyst_2/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.