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[/] [pci/] [tags/] [asyst_2/] - Rev 81

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Rev Log message Author Age Path
81 Updated synchronization in top level fifo modules. mihad 7852d 14h /pci/tags/asyst_2/
79 Updated. mihad 7855d 19h /pci/tags/asyst_2/
78 Old files with wrong names removed. mihad 7855d 19h /pci/tags/asyst_2/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7855d 19h /pci/tags/asyst_2/
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7858d 18h /pci/tags/asyst_2/
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7861d 19h /pci/tags/asyst_2/
73 Bug fixes, testcases added. mihad 7861d 20h /pci/tags/asyst_2/
72 *** empty log message *** mihad 7908d 23h /pci/tags/asyst_2/
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7916d 15h /pci/tags/asyst_2/
69 Changed BIST signal names etc.. mihad 7953d 23h /pci/tags/asyst_2/
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7957d 08h /pci/tags/asyst_2/
67 Changed BIST signals for RAMs. tadejm 7957d 13h /pci/tags/asyst_2/
66 Changed empty status generation in pciw_fifo_control.v mihad 7960d 23h /pci/tags/asyst_2/
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7963d 21h /pci/tags/asyst_2/
64 The testcase I just added in previous revision repaired mihad 7964d 00h /pci/tags/asyst_2/
63 Added additional testcase and changed rst name in BIST to trst mihad 7964d 02h /pci/tags/asyst_2/
62 Added BIST signals for RAMs. mihad 7966d 18h /pci/tags/asyst_2/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7974d 18h /pci/tags/asyst_2/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7974d 20h /pci/tags/asyst_2/
58 Removed all logic from asynchronous reset network mihad 7979d 20h /pci/tags/asyst_2/

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