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[/] [pci/] [tags/] [asyst_2/] - Rev 81

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Rev Log message Author Age Path
81 Updated synchronization in top level fifo modules. mihad 7851d 05h /pci/tags/asyst_2/
79 Updated. mihad 7854d 10h /pci/tags/asyst_2/
78 Old files with wrong names removed. mihad 7854d 10h /pci/tags/asyst_2/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7854d 10h /pci/tags/asyst_2/
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7857d 10h /pci/tags/asyst_2/
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7860d 11h /pci/tags/asyst_2/
73 Bug fixes, testcases added. mihad 7860d 11h /pci/tags/asyst_2/
72 *** empty log message *** mihad 7907d 15h /pci/tags/asyst_2/
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7915d 07h /pci/tags/asyst_2/
69 Changed BIST signal names etc.. mihad 7952d 14h /pci/tags/asyst_2/
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7956d 00h /pci/tags/asyst_2/
67 Changed BIST signals for RAMs. tadejm 7956d 04h /pci/tags/asyst_2/
66 Changed empty status generation in pciw_fifo_control.v mihad 7959d 15h /pci/tags/asyst_2/
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7962d 13h /pci/tags/asyst_2/
64 The testcase I just added in previous revision repaired mihad 7962d 15h /pci/tags/asyst_2/
63 Added additional testcase and changed rst name in BIST to trst mihad 7962d 17h /pci/tags/asyst_2/
62 Added BIST signals for RAMs. mihad 7965d 10h /pci/tags/asyst_2/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7973d 10h /pci/tags/asyst_2/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7973d 11h /pci/tags/asyst_2/
58 Removed all logic from asynchronous reset network mihad 7978d 11h /pci/tags/asyst_2/

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