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[/] [pci/] [tags/] [asyst_2/] - Rev 90

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Rev Log message Author Age Path
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7731d 16h /pci/tags/asyst_2/
89 Burst 2 error fixed. mihad 7767d 17h /pci/tags/asyst_2/
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7773d 16h /pci/tags/asyst_2/
87 Updated acording to RTL changes. mihad 7785d 14h /pci/tags/asyst_2/
86 Entered the option to disable no response counter in wb master. mihad 7785d 14h /pci/tags/asyst_2/
85 Changed Vendor ID defines. mihad 7785d 18h /pci/tags/asyst_2/
84 Changed vendor ID. mihad 7789d 12h /pci/tags/asyst_2/
83 Cleaned up the code. No functional changes. mihad 7814d 11h /pci/tags/asyst_2/
81 Updated synchronization in top level fifo modules. mihad 7828d 07h /pci/tags/asyst_2/
79 Updated. mihad 7831d 12h /pci/tags/asyst_2/
78 Old files with wrong names removed. mihad 7831d 12h /pci/tags/asyst_2/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7831d 12h /pci/tags/asyst_2/
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7834d 12h /pci/tags/asyst_2/
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7837d 13h /pci/tags/asyst_2/
73 Bug fixes, testcases added. mihad 7837d 13h /pci/tags/asyst_2/
72 *** empty log message *** mihad 7884d 17h /pci/tags/asyst_2/
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7892d 09h /pci/tags/asyst_2/
69 Changed BIST signal names etc.. mihad 7929d 16h /pci/tags/asyst_2/
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7933d 02h /pci/tags/asyst_2/
67 Changed BIST signals for RAMs. tadejm 7933d 06h /pci/tags/asyst_2/

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