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[/] [pci/] [tags/] [asyst_2/] - Rev 96

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Rev Log message Author Age Path
96 Update! mihad 7718d 14h /pci/tags/asyst_2/
95 Removed this file, because it was too large - long download time. mihad 7718d 14h /pci/tags/asyst_2/
94 Changed one critical PCI bus signal logic. mihad 7718d 14h /pci/tags/asyst_2/
93 Added a test application! mihad 7718d 21h /pci/tags/asyst_2/
92 Update! mihad 7718d 22h /pci/tags/asyst_2/
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7754d 12h /pci/tags/asyst_2/
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7754d 12h /pci/tags/asyst_2/
89 Burst 2 error fixed. mihad 7790d 12h /pci/tags/asyst_2/
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7796d 11h /pci/tags/asyst_2/
87 Updated acording to RTL changes. mihad 7808d 09h /pci/tags/asyst_2/
86 Entered the option to disable no response counter in wb master. mihad 7808d 09h /pci/tags/asyst_2/
85 Changed Vendor ID defines. mihad 7808d 13h /pci/tags/asyst_2/
84 Changed vendor ID. mihad 7812d 07h /pci/tags/asyst_2/
83 Cleaned up the code. No functional changes. mihad 7837d 06h /pci/tags/asyst_2/
81 Updated synchronization in top level fifo modules. mihad 7851d 02h /pci/tags/asyst_2/
79 Updated. mihad 7854d 07h /pci/tags/asyst_2/
78 Old files with wrong names removed. mihad 7854d 08h /pci/tags/asyst_2/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7854d 08h /pci/tags/asyst_2/
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7857d 07h /pci/tags/asyst_2/
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7860d 08h /pci/tags/asyst_2/

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