URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [asyst_2/] [rtl/] [verilog/] - Rev 104

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
104	Found and simulated the problem in the synchronization logic. Repaired the synchronization logic in the FIFOs.	mihad	7634d 00h	/pci/tags/asyst_2/rtl/verilog/
94	Changed one critical PCI bus signal logic.	mihad	7680d 22h	/pci/tags/asyst_2/rtl/verilog/
88	Added the reset value parameter to the synchronizer flop module. Added resets to all synchronizer flop instances. Repaired initial sync value in fifos.	mihad	7758d 19h	/pci/tags/asyst_2/rtl/verilog/
86	Entered the option to disable no response counter in wb master.	mihad	7770d 17h	/pci/tags/asyst_2/rtl/verilog/
83	Cleaned up the code. No functional changes.	mihad	7799d 14h	/pci/tags/asyst_2/rtl/verilog/
81	Updated synchronization in top level fifo modules.	mihad	7813d 10h	/pci/tags/asyst_2/rtl/verilog/
79	Updated.	mihad	7816d 15h	/pci/tags/asyst_2/rtl/verilog/
78	Old files with wrong names removed.	mihad	7816d 15h	/pci/tags/asyst_2/rtl/verilog/
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7816d 15h	/pci/tags/asyst_2/rtl/verilog/
73	Bug fixes, testcases added.	mihad	7822d 16h	/pci/tags/asyst_2/rtl/verilog/
72	* empty log message *	mihad	7869d 20h	/pci/tags/asyst_2/rtl/verilog/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7877d 12h	/pci/tags/asyst_2/rtl/verilog/
69	Changed BIST signal names etc..	mihad	7914d 19h	/pci/tags/asyst_2/rtl/verilog/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7918d 05h	/pci/tags/asyst_2/rtl/verilog/
67	Changed BIST signals for RAMs.	tadejm	7918d 09h	/pci/tags/asyst_2/rtl/verilog/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7921d 20h	/pci/tags/asyst_2/rtl/verilog/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7924d 18h	/pci/tags/asyst_2/rtl/verilog/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7924d 22h	/pci/tags/asyst_2/rtl/verilog/
62	Added BIST signals for RAMs.	mihad	7927d 15h	/pci/tags/asyst_2/rtl/verilog/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7935d 15h	/pci/tags/asyst_2/rtl/verilog/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories pci

[/] [pci/] [tags/] [asyst_2/] [rtl/] [verilog/] - Rev 104

Filtering Options