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[/] [pci/] [tags/] [asyst_2/] [rtl/] [verilog/] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5583d 17h /pci/tags/asyst_2/rtl/verilog/
133 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 7491d 14h /pci/tags/asyst_2/rtl/verilog/
132 Compact PCI Hot Swap support added.
New testcases added.
Specification updated.
Test application changed to support WB B3 cycles.		 mihad 7491d 14h /pci/tags/asyst_2/rtl/verilog/
131 Moved top.v to bench directory. Removed unneeded meta_flop,
modified files list files accordingly.		 mihad 7495d 13h /pci/tags/asyst_2/rtl/verilog/
130 The wbs B3 to B2 translation logic had wrong reset wire connected! mihad 7500d 13h /pci/tags/asyst_2/rtl/verilog/
128 Some warning cleanup. simons 7501d 16h /pci/tags/asyst_2/rtl/verilog/
126 ifdef - endif statements put in separate lines for flint compatibility. simons 7509d 09h /pci/tags/asyst_2/rtl/verilog/
124 Added missing signals to 2 sensitivity lists. Everything works the same as before. tadejm 7547d 16h /pci/tags/asyst_2/rtl/verilog/
122 mbist signals updated according to newest convention markom 7554d 16h /pci/tags/asyst_2/rtl/verilog/
117 WB Master is now WISHBONE B3 compatible. tadejm 7611d 04h /pci/tags/asyst_2/rtl/verilog/
116 Corrected bug when writing to FIFO (now it is registered). tadejm 7611d 05h /pci/tags/asyst_2/rtl/verilog/
115 Added signals for WB Master B3. tadejm 7611d 05h /pci/tags/asyst_2/rtl/verilog/
113 ifdefs moved to thier own lines, this confuses some of the tools. simons 7618d 07h /pci/tags/asyst_2/rtl/verilog/
111 synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. simons 7618d 12h /pci/tags/asyst_2/rtl/verilog/
110 Module that converts slave WISHBONE B3 accesses to
WISHBONE B2 accesses with CAB.		 mihad 7620d 11h /pci/tags/asyst_2/rtl/verilog/
108 Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. tadejm 7624d 09h /pci/tags/asyst_2/rtl/verilog/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7629d 07h /pci/tags/asyst_2/rtl/verilog/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7634d 17h /pci/tags/asyst_2/rtl/verilog/
94 Changed one critical PCI bus signal logic. mihad 7681d 15h /pci/tags/asyst_2/rtl/verilog/
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7759d 12h /pci/tags/asyst_2/rtl/verilog/

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