OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [asyst_2/] [rtl/] [verilog/] - Rev 53

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 8000d 01h /pci/tags/asyst_2/rtl/verilog/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 8000d 05h /pci/tags/asyst_2/rtl/verilog/
50 Got rid of undef directives mihad 8002d 21h /pci/tags/asyst_2/rtl/verilog/
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 8002d 21h /pci/tags/asyst_2/rtl/verilog/
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 8002d 21h /pci/tags/asyst_2/rtl/verilog/
47 Known issues repaired mihad 8003d 03h /pci/tags/asyst_2/rtl/verilog/
46 Include statement was enclosed in synosys translate off/on directive - repaired mihad 8007d 22h /pci/tags/asyst_2/rtl/verilog/
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 8009d 03h /pci/tags/asyst_2/rtl/verilog/
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8154d 07h /pci/tags/asyst_2/rtl/verilog/
33 Added some testcases, removed un-needed fifo signals mihad 8170d 02h /pci/tags/asyst_2/rtl/verilog/
32 Added include statement that was missing and causing errors mihad 8177d 23h /pci/tags/asyst_2/rtl/verilog/
26 Modified testbench and fixed some bugs mihad 8183d 22h /pci/tags/asyst_2/rtl/verilog/
23 *** empty log message *** mihad 8201d 22h /pci/tags/asyst_2/rtl/verilog/
21 Repaired a few bugs, updated specification, added test bench files and design document mihad 8201d 23h /pci/tags/asyst_2/rtl/verilog/
19 *** empty log message *** mihad 8201d 23h /pci/tags/asyst_2/rtl/verilog/
18 *** empty log message *** mihad 8202d 00h /pci/tags/asyst_2/rtl/verilog/
7 Updated all files with inclusion of timescale file for simulation purposes. mihad 8321d 06h /pci/tags/asyst_2/rtl/verilog/
6 Updated all files with inclusion of timescale file for simulation purposes. mihad 8321d 06h /pci/tags/asyst_2/rtl/verilog/
2 New project directory structure mihad 8323d 23h /pci/tags/asyst_2/rtl/verilog/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.