URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [asyst_2/] [rtl/] [verilog/] - Rev 77

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7821d 15h	/pci/tags/asyst_2/rtl/verilog/
73	Bug fixes, testcases added.	mihad	7827d 15h	/pci/tags/asyst_2/rtl/verilog/
72	* empty log message *	mihad	7874d 19h	/pci/tags/asyst_2/rtl/verilog/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7882d 11h	/pci/tags/asyst_2/rtl/verilog/
69	Changed BIST signal names etc..	mihad	7919d 18h	/pci/tags/asyst_2/rtl/verilog/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7923d 04h	/pci/tags/asyst_2/rtl/verilog/
67	Changed BIST signals for RAMs.	tadejm	7923d 09h	/pci/tags/asyst_2/rtl/verilog/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7926d 19h	/pci/tags/asyst_2/rtl/verilog/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7929d 17h	/pci/tags/asyst_2/rtl/verilog/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7929d 21h	/pci/tags/asyst_2/rtl/verilog/
62	Added BIST signals for RAMs.	mihad	7932d 14h	/pci/tags/asyst_2/rtl/verilog/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7940d 14h	/pci/tags/asyst_2/rtl/verilog/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7940d 16h	/pci/tags/asyst_2/rtl/verilog/
58	Removed all logic from asynchronous reset network	mihad	7945d 16h	/pci/tags/asyst_2/rtl/verilog/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7945d 22h	/pci/tags/asyst_2/rtl/verilog/
56	Number of state bits define was removed	mihad	7946d 12h	/pci/tags/asyst_2/rtl/verilog/
55	Changed state machine encoding to true one-hot	mihad	7946d 13h	/pci/tags/asyst_2/rtl/verilog/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	7979d 18h	/pci/tags/asyst_2/rtl/verilog/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	7979d 22h	/pci/tags/asyst_2/rtl/verilog/
50	Got rid of undef directives	mihad	7982d 15h	/pci/tags/asyst_2/rtl/verilog/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories pci

[/] [pci/] [tags/] [asyst_2/] [rtl/] [verilog/] - Rev 77

Filtering Options