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[/] [pci/] [tags/] [asyst_3/] - Rev 105

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Rev Log message Author Age Path
105 Wrong pci_bridge32.v file included in the project! mihad 7630d 17h /pci/tags/asyst_3/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7630d 20h /pci/tags/asyst_3/
103 Added test application and modified files to support it. mihad 7677d 17h /pci/tags/asyst_3/
102 Cleanup! mihad 7677d 17h /pci/tags/asyst_3/
101 Added simulation files. mihad 7677d 17h /pci/tags/asyst_3/
100 Cleanup! mihad 7677d 17h /pci/tags/asyst_3/
99 Cleanup! mihad 7677d 18h /pci/tags/asyst_3/
98 Cleanup. mihad 7677d 18h /pci/tags/asyst_3/
97 Doing a little bit of cleanup. mihad 7677d 18h /pci/tags/asyst_3/
96 Update! mihad 7677d 18h /pci/tags/asyst_3/
95 Removed this file, because it was too large - long download time. mihad 7677d 18h /pci/tags/asyst_3/
94 Changed one critical PCI bus signal logic. mihad 7677d 18h /pci/tags/asyst_3/
93 Added a test application! mihad 7678d 01h /pci/tags/asyst_3/
92 Update! mihad 7678d 02h /pci/tags/asyst_3/
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7713d 15h /pci/tags/asyst_3/
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7713d 15h /pci/tags/asyst_3/
89 Burst 2 error fixed. mihad 7749d 16h /pci/tags/asyst_3/
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7755d 15h /pci/tags/asyst_3/
87 Updated acording to RTL changes. mihad 7767d 13h /pci/tags/asyst_3/
86 Entered the option to disable no response counter in wb master. mihad 7767d 13h /pci/tags/asyst_3/

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