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[/] [pci/] [tags/] [asyst_3/] [rtl/] - Rev 55

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Rev	Log message	Author	Age	Path
55	Changed state machine encoding to true one-hot	mihad	7953d 04h	/pci/tags/asyst_3/rtl/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	7986d 10h	/pci/tags/asyst_3/rtl/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	7986d 14h	/pci/tags/asyst_3/rtl/
50	Got rid of undef directives	mihad	7989d 06h	/pci/tags/asyst_3/rtl/
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	7989d 06h	/pci/tags/asyst_3/rtl/
48	Extracted distributed RAM module from wb/pci_tpram.v to its own file	mihad	7989d 06h	/pci/tags/asyst_3/rtl/
47	Known issues repaired	mihad	7989d 12h	/pci/tags/asyst_3/rtl/
46	Include statement was enclosed in synosys translate off/on directive - repaired	mihad	7994d 06h	/pci/tags/asyst_3/rtl/
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	7995d 12h	/pci/tags/asyst_3/rtl/
35	Files updated with missing includes, resolved some race conditions in test bench	mihad	8140d 15h	/pci/tags/asyst_3/rtl/
33	Added some testcases, removed un-needed fifo signals	mihad	8156d 11h	/pci/tags/asyst_3/rtl/
32	Added include statement that was missing and causing errors	mihad	8164d 08h	/pci/tags/asyst_3/rtl/
26	Modified testbench and fixed some bugs	mihad	8170d 06h	/pci/tags/asyst_3/rtl/
23	* empty log message *	mihad	8188d 07h	/pci/tags/asyst_3/rtl/
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8188d 08h	/pci/tags/asyst_3/rtl/
19	* empty log message *	mihad	8188d 08h	/pci/tags/asyst_3/rtl/
18	* empty log message *	mihad	8188d 08h	/pci/tags/asyst_3/rtl/
7	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8307d 15h	/pci/tags/asyst_3/rtl/
6	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8307d 15h	/pci/tags/asyst_3/rtl/
2	New project directory structure	mihad	8310d 07h	/pci/tags/asyst_3/rtl/

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[/] [pci/] [tags/] [asyst_3/] [rtl/] - Rev 55

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