URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [asyst_3/] [rtl/] [verilog/] - Rev 59

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7966d 17h	/pci/tags/asyst_3/rtl/verilog/
58	Removed all logic from asynchronous reset network	mihad	7971d 17h	/pci/tags/asyst_3/rtl/verilog/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7971d 23h	/pci/tags/asyst_3/rtl/verilog/
56	Number of state bits define was removed	mihad	7972d 13h	/pci/tags/asyst_3/rtl/verilog/
55	Changed state machine encoding to true one-hot	mihad	7972d 14h	/pci/tags/asyst_3/rtl/verilog/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	8005d 19h	/pci/tags/asyst_3/rtl/verilog/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	8005d 23h	/pci/tags/asyst_3/rtl/verilog/
50	Got rid of undef directives	mihad	8008d 16h	/pci/tags/asyst_3/rtl/verilog/
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	8008d 16h	/pci/tags/asyst_3/rtl/verilog/
48	Extracted distributed RAM module from wb/pci_tpram.v to its own file	mihad	8008d 16h	/pci/tags/asyst_3/rtl/verilog/
47	Known issues repaired	mihad	8008d 22h	/pci/tags/asyst_3/rtl/verilog/
46	Include statement was enclosed in synosys translate off/on directive - repaired	mihad	8013d 16h	/pci/tags/asyst_3/rtl/verilog/
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	8014d 22h	/pci/tags/asyst_3/rtl/verilog/
35	Files updated with missing includes, resolved some race conditions in test bench	mihad	8160d 01h	/pci/tags/asyst_3/rtl/verilog/
33	Added some testcases, removed un-needed fifo signals	mihad	8175d 21h	/pci/tags/asyst_3/rtl/verilog/
32	Added include statement that was missing and causing errors	mihad	8183d 17h	/pci/tags/asyst_3/rtl/verilog/
26	Modified testbench and fixed some bugs	mihad	8189d 16h	/pci/tags/asyst_3/rtl/verilog/
23	* empty log message *	mihad	8207d 17h	/pci/tags/asyst_3/rtl/verilog/
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8207d 17h	/pci/tags/asyst_3/rtl/verilog/
19	* empty log message *	mihad	8207d 17h	/pci/tags/asyst_3/rtl/verilog/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories pci

[/] [pci/] [tags/] [asyst_3/] [rtl/] [verilog/] - Rev 59

Filtering Options