URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [asyst_3/] [rtl/] [verilog/] - Rev 66

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
66	Changed empty status generation in pciw_fifo_control.v	mihad	7986d 14h	/pci/tags/asyst_3/rtl/verilog/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7989d 12h	/pci/tags/asyst_3/rtl/verilog/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7989d 16h	/pci/tags/asyst_3/rtl/verilog/
62	Added BIST signals for RAMs.	mihad	7992d 09h	/pci/tags/asyst_3/rtl/verilog/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	8000d 09h	/pci/tags/asyst_3/rtl/verilog/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	8000d 10h	/pci/tags/asyst_3/rtl/verilog/
58	Removed all logic from asynchronous reset network	mihad	8005d 11h	/pci/tags/asyst_3/rtl/verilog/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	8005d 17h	/pci/tags/asyst_3/rtl/verilog/
56	Number of state bits define was removed	mihad	8006d 07h	/pci/tags/asyst_3/rtl/verilog/
55	Changed state machine encoding to true one-hot	mihad	8006d 08h	/pci/tags/asyst_3/rtl/verilog/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	8039d 13h	/pci/tags/asyst_3/rtl/verilog/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	8039d 17h	/pci/tags/asyst_3/rtl/verilog/
50	Got rid of undef directives	mihad	8042d 10h	/pci/tags/asyst_3/rtl/verilog/
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	8042d 10h	/pci/tags/asyst_3/rtl/verilog/
48	Extracted distributed RAM module from wb/pci_tpram.v to its own file	mihad	8042d 10h	/pci/tags/asyst_3/rtl/verilog/
47	Known issues repaired	mihad	8042d 15h	/pci/tags/asyst_3/rtl/verilog/
46	Include statement was enclosed in synosys translate off/on directive - repaired	mihad	8047d 10h	/pci/tags/asyst_3/rtl/verilog/
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	8048d 15h	/pci/tags/asyst_3/rtl/verilog/
35	Files updated with missing includes, resolved some race conditions in test bench	mihad	8193d 19h	/pci/tags/asyst_3/rtl/verilog/
33	Added some testcases, removed un-needed fifo signals	mihad	8209d 15h	/pci/tags/asyst_3/rtl/verilog/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories pci

[/] [pci/] [tags/] [asyst_3/] [rtl/] [verilog/] - Rev 66

Filtering Options